Alterable capacitor memory array

Claim 1

A non-volatile semiconductor memory system comprising: a rectangular array of non-volatile, alterable threshold capacitors disposed on a single semiconductor substrate and comprising a plurality of parallel source stripes formed in the substrate, and a plurality of non-volatile, alterable-threshold capacitor devices formed on said substrate in a plurality of columns each immediately adjacent one of said source stripes, each of said capacitor devices comprising dual gate insulator layers of thin silicon oxide and silicon nitride and a conductive gate element connected in common along each common gate row of said capacitor devices, and each of said capacitor devices being selectably preprogrammed to one of first and second threshold voltage states having associated first lower and second higher capacitance values by application of selected signals to substrate, source stripe and gate element; and reading means comprising read signal means for applying a read voltage to a selected row of said capacitor devices, reference signal means for supplying a reference signal voltage, at least one differential sensing circuit receiving said reference signal voltage, and coupling means for operatively coupling said differential sensing circuit between a selected one of said source stripes and an output terminal, said read voltage having a magnitude at least equal to said second threshold voltage to couple a charge of first or second magnitude to said source stripe depending on whether the capacitor device associated with said selected row and selected source stripe is in said first or second threshold voltage state, said differential sensing circuit comparing the voltage induced on said selected source stripe by said charge with said reference voltage to produce an output of a first value if said induced voltage is greater than said reference voltage and a second value if said induced voltage is less than said reference voltage.