US4093942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Matrix circuits
Assignee: Toshiba Corp
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Filing: 1976-06-04
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Granted: 1978-06-06
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Expires: 1996-06-04
Abstract
Abstract A matrix circuit acting as a read only memory (ROM) comprises first and second groups of input lines, a third group of input lines arranged between the first and second groups of input lines, a plurality of groups of output lines intersecting the input lines off the first, second and third group, each group of the output lines having one terminal commonly connected in a wired OR fasion to one end of a power source and having the other terminal commonly connected to the ground. A plurality of first switching elements are respectively connected to the output lines and selectively driven by an input signal supplied to the first group of the input lines, a plurality of second switching elements driven by the same input signal as that supplied to the first switching elements and respectively connected to the output lines each lying adjacent to the output lines connected with the first switching elements, and a plurality of third switching elements respectively connected between the adjacent output lines and selectively driven by an input signal supplied to the third group of input lines.
Inventors
- 👤 Yasoji Suzuki
- 👤 Yoshio Kaneko
- 👤 Yoshihisa Shiotari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:55
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H03; H03M; H03M7/00; H03M7/001; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
223 words
A read-only memory matrix circuit comprising: a first group of input lines, a second group of input lines, a third group of input lines and a plurality of groups of output lines intersecting the input lines of the first, second and third groups to form a matrix array, the third group of input lines being arranged in the matrix array between the first and second groups of input lines, each of the plurality of groups of output lines having a common terminal connected to one end of a power source and another common terminal connected to ground, a plurality of first switching elements, individual ones of the plurality of first switching elements being connected to respective output lines and being selectively driven by first input signals applied to the input lines forming said first group, a plurality of second switching elements, respective ones of which are driven by the same first input signals applied to the plurality of first switching elements and are connected to the output lines consecutively located next in the matrix array relative to the output lines in which the first switching elements are connected, and a plurality of third switching elements, individual ones of which form different combinations connected between adjacent output lines and are selectively driven by second input signals applied to the third group of input lines.
Claim 2
Dependent Claim
223 words
A read-only memory matrix circuit comprising: a first group of input lines, a second group of input lines, a third group of input lines and a plurality of groups of output lines intersecting the input lines of the first, second and third groups to form a matrix array, the third group of input lines being arranged in the matrix array between the first and second groups of input lines, each of the plurality of groups of output lines having a common terminal connected to one end of a power source and another common terminal connected to ground, a plurality of first switching elements, individual ones of the plurality of first switching elements being connected to respective output lines and being selectively driven by first input signals applied to the input lines forming said first group, a plurality of second switching elements, respective ones of which are driven by the same first input signals applied to the plurality of first switching elements and are connected to the output lines consecutively located next in the matrix array relative to the output lines in which the first switching elements are connected, and a plurality of third switching elements, individual ones of which form different combinations connected between adjacent output lines and are selectively driven by second input signals applied to the third group of input lines.
Claim 3
Dependent Claim
35 words
A matrix circuit according to claim 1 wherein said common terminal of each of the plurality of groups of output lines is connected to the one end of the power source through a wired-OR connection.
Claim 4
Dependent Claim
47 words
A matrix circuit according to claim 1 wherein the matrix circuit further comprises at least one further output line arranged at one end portion of the matrix array constituted by said plurality of groups of output lines and adapted to be used only as a ground line.
Claim 5
Dependent Claim
65 words
A matrix circuit according to claim 1 wherein said common terminal of each of the plurality of groups of output lines is connected to the power source through a load MOS element of one conductivity type channel, said first, second and third switching elements are MOS FET elements of another conductivity type channel, and clock pulse signals are supplied between the common terminal and ground.
Claim 6
Dependent Claim
30 words
A matrix circuit according to claim 1 wherein said common terminal of each of the plurality of groups of output lines is connected to the power source through a diode.
Claim 7
Dependent Claim
30 words
A matrix circuit according to claim 1 wherein said common terminal of each of the plurality of groups of output lines is connected to the power source through a resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-05 | 1981-12-05 | 1982-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-05 | 1985-12-05 | 1986-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-05 | 1989-12-05 | 1990-06-06 | $7700.00 | Window Closed / Lapsed |