Two-dimensional photodiode matrix array

Claim 2

An integrated circuit array comprising: a plurality of photodiodes arranged in rows and columns, said plurality of photodiodes being arranged in groups of four, the photodiodes in each group of four being located in two rows and two columns such that each photodiode is located uniquely at the intersection of one of said two rows and one of said two columns, a multiplicity of insulated-gate field-effect transistor switches arranged in rows and columns, said field-effect transistor switches being arranged in pairs, each pair of switches being located in one column and two rows and being uniquely connected to a corresponding group of four photodiodes such that the first transistor switch in said pair is capable of passing signals generated by the two photodiodes in said group located in one row and the second transistor switch in said pair is capable of passing signals generated by the two photodiodes in said group located in the other row, each row of said field-effect transistor switches corresponding uniquely to one row of said photodiodes; means for applying energizing potential to any column of said photodiodes to render the photodiodes in said column operative; means for selectively applying energizing potential to any row of said field-effect transistor switches thereby to energize the photodiode corresponding to the column and the row which are energized; and means, coupled to said switches, for deriving an output from said energized photodiode.

Claim 3

Structure as in claim 1 wherein each of said plurality of photodiodes comprises a photosensitive source region, a drain region, a gate electrode overlying but insulated from the semiconductor material between said source region and said drain region and a drain electrode electrically coupled to said drain region.

Claim 4

Structure as in claim 2 wherein said gate electrodes in each column of said photodiodes are connected by a common electrode uniquely associated with that column to said means for selectively applying energizing potential to any column.

Claim 5

StructurE as in claim 3 wherein each of said insulated-gate field-effect transistor switches comprises: a source region; a drain region separated from said source region by semiconductor material; a gate electrode overlying but insulated from the semiconductor material between said source region and said drain region; a source electrode contacting said source region; a drain electrode contacting said drain region; and wherein said source electrode of said insulated-gate field-effect transistor switch is connected to the drain electrodes of the two selected photodiodes in the corresponding group of photodiodes in one row.

Claim 6

Structure as in claim 4 wherein said gate electrodes in each row of said transistor switches are connected by a common electrode uniquely associated with that row to said means for selectively applying energizing potential to any row.

Claim 7

Structure as in claim 5 wherein; a common electrode connects the drains of each successive pair of field-effect transistor switches in two adjacent rows of said switches to said means for deriving an output from said energized photodiode.

Claim 8

An integrated circuit array comprising: a substrate, a plurality of separate zones on said substrate arranged in spaced-apart rows and columns, each zone comprising four photodevices, each photodevice having a source region and a drain region separated by semiconductor material, a gate electrode overlying but insulated from said semiconductor material and a drain electrode connected to said drain region, and two insulated-gate field-effect transistors, each field-effect transistor having a source region and a drain region separated by semiconductor material, a gate electrode overlying but insulated from said semiconductor material, a source electrode attached to said source region and a drain electrode attached to said drain region, the gates of a first and third of said photodevices being coupled together and the gates of a second and fourth of said photodevices being coupled together, the drains of said first and second photodevices being coupled to the source of a first one of said field-effect transistors, the drains of said third and fourth photodevices being coupled to the source of the second one of said field-effect transistors, the drains of said two field-effect transistors being coupled together, means for interconnecting the gate electrodes of the first and third photodevices in all zones in the same column, means for interconnecting the gate electrodes of the second and fourth photodevices in all zones in the same column, means for interconnecting the gate electrodes of the first field-effect transistors in all the zones in the same row, means for interconnecting the gate electrodes of the second field-effect transistors in all zones in the same row, and contact means for coupling the drain electrodes of all field-effect transistors to an output means.

Claim 9

An integrated circuit array comprising: a substrate, a plurality of separate zones on said substrate arranged in spaced-apart rows and columns, each zone comprising four photodevices, each photodevice having a source region and a drain region separated by semiconductor material, a gate electrode overlying but insulated from said semiconductor material and a drain electrode connected to said drain region, and two insulated-gate field-effect transistors, each field-effect transistor having a source region and a drain region separated by semiconductor material, a gate electrode overlying but insulated from said semiconductor material, a source electrode attached to said source region and a drain electrode attached to said drain region, the gates of a first and third of said photodevices being coupled together and the gates of a second and fourth of said photodevices being coupled together, the drains of said first and second photodevices being coupled to the source of a first one of said field-effect transistors, the drains of said third and fourth photodevices being coupled to the source of the second one of said field-effect transistors, the drains of said two field-effect transistors being coupled together, means for interconnecting the gate electrodes of the first and third photodevices in all zones in the same column, means for interconnecting the gate electrodes of the second and fourth photodevices in all zones in the same column, means for interconnecting the gate electrodes of the first field-effect transistors in all the zones in the same row, means for interconnecting the gate electrodes of the second field-effect transistors in all zones in the same row, and contact means for coupling the drain electrodes of all field-effect transistors to an output means.

Claim 10

An integrated circuit array as claimed in claim 7 wherein said substrate is silicon and the gates of said switches and said photodiodes comprise heavily doped silicon insulated from said substrate by silicon oxide.

Claim 11

An integrated-circuit array comprising a substrate, a plurality of separate zones on said substrate in spaced-apart rows and columns, each zone being arranged in quadrants with a photodiode structure in each quadrant and two insulated-gate field-effect transistor switch structures, a first switch being connected to the photodiodes in a first and second quadrant and the second switch being connected to the photodiodes in a third and a fourth quadrant, the structures in said first and second quadrants and in said third and fourth quadrants each comprising, in series, a diffused source region for one of the photodiodes, an insulated gate for said one photodiode, the insulated gate of the photodiode in the first quadrant being interconnected with the insulated gate of the photodiode in the third quadrAnt, a diffused region serving as the drain for said one photodiode and a portion of the source for the associated first switch, a first insulated gate structure for the first switch, a diffused region for the drain of the first switch, said drain region being common for both switches, a second insulated gate structure for the second switch interconnected with said first insulated gate structure, a diffused region serving as another portion of the source for the associated first switch and the drain for the other one of the photodiodes, and insulated gate for the other photodiode, the insulated gate of the photodiode in the second quadrant being interconnected with the insulated gate of the photodiode in the fourth quadrant, and a diffused photodiode source region for another one of the photodiodes.

Claim 12

An integrated-circuit array comprising a substrate, a plurality of separate zones on said substrate in spaced-apart rows and columns, each zone being arranged in quadrants with a photodiode structure in each quadrant and two insulated-gate field-effect transistor switch structures, a first switch being connected to the photodiodes in a first and second quadrant and the second switch being connected to the photodiodes in a third and a fourth quadrant, the structures in said first and second quadrants and in said third and fourth quadrants each comprising, in series, a diffused source region for one of the photodiodes, an insulated gate for said one photodiode, the insulated gate of the photodiode in the first quadrant being interconnected with the insulated gate of the photodiode in the third quadrAnt, a diffused region serving as the drain for said one photodiode and a portion of the source for the associated first switch, a first insulated gate structure for the first switch, a diffused region for the drain of the first switch, said drain region being common for both switches, a second insulated gate structure for the second switch interconnected with said first insulated gate structure, a diffused region serving as another portion of the source for the associated first switch and the drain for the other one of the photodiodes, and insulated gate for the other photodiode, the insulated gate of the photodiode in the second quadrant being interconnected with the insulated gate of the photodiode in the fourth quadrant, and a diffused photodiode source region for another one of the photodiodes.

Claim 13

An integrated circuit array as claimed in claim 9 wherein said substrate is silicon and the gates of said switches and photodiodes comprise heavily doped silicon insulated from said substrate by silicon dioxide.

Claim 14

An integrated circuit array as claimed in claim 9 including means for interconnecting the insulated gates of the photodiodes in the first and third quadrants with the insulated gates of associated photodiodes in the first and third quadrant of certain other zones, means for interconnecting the insulated gates of the photodiodes in the second and fourth quadrants with the insulated gates of associated photodiodes in the second and fourth quadrants of certain other zones, means for interconnecting the gate of said first switch to the gates of associated switches in certain other zones, means for interconnecting the gate of said second switch to the gates of associated switches in certain other zones, and contact means for connecting with the common drain region of the said switches.

Claim 15

An integrated-circuit array as claimed in claim 11 wherein said substrate is silicon and the gates of said switches and said photodiodes comprise heavily doped silicon insulated from said substrate by silicon dioxide.

Claim 16

An integrated-circuit array comprising a substrate, a plurality of separate zones on said substrate arranged in spaced-apart rows and columns, each zone having two pairs of photodiodes and two insulated-gate field-effect transistor switch structures, one switch being associated with the first pair of photodiodes and the second switch being associated with the second pair of photodiodes each pair of diodes and its associated switch comprising a diffused source region for one of the photodiodes, an insulated gate for said one photodiode, the insulated gate of said one photodiode in the first pair being interconnected with the insulated gate of one photodiode in the second pair, a diffused region serving as the drain for said one photodiode and a portion of the source for the associated switch, an insulated gate for the switch, a diffused region for the drain of the switch, said drain region being common for both switches, a diffused region serving as another portion of the source for the associated switch and the drain for the other one of the photodiodes in said pair, an insulated gate for the other photodiode, the insulated gate of the other photodiode in the first pair being interconnected with the insulated gate of the second photodiode in the second pair, and a diffused photodiode source region for the second one of the photodiodes.

Claim 17

An integrated-circuit array comprising a substrate, a plurality of separate zones on said substrate arranged in spaced-apart rows and columns, each zone having two pairs of photodiodes and two insulated-gate field-effect transistor switch structures, one switch being associated with the first pair of photodiodes and the second switch being associated with the second pair of photodiodes each pair of diodes and its associated switch comprising a diffused source region for one of the photodiodes, an insulated gate for said one photodiode, the insulated gate of said one photodiode in the first pair being interconnected with the insulated gate of one photodiode in the second pair, a diffused region serving as the drain for said one photodiode and a portion of the source for the associated switch, an insulated gate for the switch, a diffused region for the drain of the switch, said drain region being common for both switches, a diffused region serving as another portion of the source for the associated switch and the drain for the other one of the photodiodes in said pair, an insulated gate for the other photodiode, the insulated gate of the other photodiode in the first pair being interconnected with the insulated gate of the second photodiode in the second pair, and a diffused photodiode source region for the second one of the photodiodes.

Claim 18

An integrated-circuit array as claimed in claim 13 wherein said substrate is silicon and the gates of said switches and photodiodes comprise heavily doped silicon insulated from said substrate by silicon dioxide.

Claim 19

An integrated circuit array as claimed in claim 13 including means for interconnecting the insulated gates of said one photodiodes in the first and second pair with the insulated gates of associated photodiodes in the first and second pairs of photodiodes of certain other zones, means for interconnecting the insulated gates of said other photodiodes in the first and second pair with the insulated gatEs of associated photodiodes in the first and second pairs of photodiodes of certain other zones, means for interconnecting the gate of said one switch to the gates of associated switches in certain other zones, means for interconnecting the gate of said second switch to the gates of associated switches in certain other zones, and contact means for connecting with the common drain region of said switches.