Programmable binary amplifier

Claim 2

In a data decoding system for decoding data signals read from magnetic tape, the magnetic tape including first reference signals recorded thereon at the beginning of the tape, the improvement comprising: amplifier means for receiving said first reference signals and said data signals read from the tape for amplifying said signals, said amplifier means including a plurality of stages of amplification for amplifying said signals, each stage having a gain of either one or A n where A is a number greater than one and where n is an integer equal to or greater than zero and selected to form a binary progression, said stages having an output signal whose gain is equal to the product of a gain of each stage of amplification; a plurality of switches corresponding in number to the number of stages of amplification with each of said switches being associated with a respective stage of amplification and coupled to each of said amplifier stages for incrementally changing the gain of each stage from one to A n when operated; a binary counter operated by said first reference signals to incrementally output a predetermined number of increasing binary numbers; decoding means coupled to said switches and said binary counter for receiving the binary output of said counter to operate said switches in accordance with the binary output of said counter wherein the amplifier gain is sequentially incremented through a number of increments corresponding to said predetermined number counted by said counter; a source of second reference signals representing a voltage level of a predetermined magnitude greater than zero; first means for comparing the output of the amplifier to a referece voltage equal to zero and having an output when the amplitude of the amplifier signal exceeds said reference voltage; second means for comparing the output of the amplifier to said second reference signals and having an output when the amplified signal exceeds said second reference signals; and means coupling the output of said second comparing means to said binary counter for inhibiting the incrementing of said counter whereby the gain of the amplifier is set at a level equal to the output of the binary counter.

Claim 3

A programmable amplifier in accordance with claim 1 wherein the number of stages of amplification are four with each stage having a gain of either 1 or A n where 1 < A < 2 and 0 ≦ n < 16.

Claim 4

A programmable amplifier in accordance with claim 2 wherein said counter comprises a sixteen bit binary counter for incrementally increasing the total amplifier gain from (A) o to (A) 15 in sixteen binary steps.

Claim 5

A programmable amplifier in accordance with claim 3 wherein each amplifier stage is a transistor amplifier and wherein the gain of the first and second stages is determined by the ratio of the collector to emitter resistance and the gain of the third and fourth stages is determined by the ratio of the emitter to collector resistance, said switches are connected to a resistance in each stage to decrease the collector resistance in said first and second stages and the emitter resistance in said third and fourth stages when operated to sequentially and incrementally increase the total amplifier gain by said binary steps.

Claim 6

A programmable amplifier in accordance with claim 4 wherein the gain of said first stage is switchable between A o and A 1 , the gain of said second stage is switchable between A o and A 2 , the gain of said third stage is switchable between A o and A 4 , and the gain of said fourth stage is switchable between A o and A 8 .

Claim 7

In a data decoding system for decoding data signals read from magnetic tape, the magnetic tape including first reference signals recorded thereon at the beginning of the tape, the improvement comprising: a multi-stage amplifier for receiving said first reference signals and said data signals read from the tape for amplifying said signals, said amplifier being programmable to assume a plurality of different gains with each of the gains of the amplifier being related in a binary sequence KA n where K is an arbitrary constant, A is the gain of one amplifier stage and n is an integer including zero; means for decoding said amplified signals for deriving a decoded data signal, said decoding means including a source of second reference signals representing a voltage level of a predetermined magnitude greater than zero; first means for comparing the output of the amplifier to a reference voltage equal to zero and having an output when the amplitude of the amplifier signal exceeds said reference voltage; second means for comparing the output of the amplifier to said second reference signals and having an output when the amplified signal exceeds said second reference signals; a binary counter operated by said first reference signals to sequentially output a plurality of increasing binary numbers; switch means coupled to the output of said binary counter for incrementally increasing the gain of the amplifier in accordance with the output of said binary counter; feedback means for coupling the output of said second comparing means to said binary counter for inhibiting the incrementing of said counter whereby the gain of the amplifier is set at a level equal to the output of the binary counter; and gating means responsive to the outputs of said first and second comparing means for gating said decoded data signals from said first comparing means through said gating means when said second comparing means has an output in coincidence therewith.

Claim 8

In a data decoding system for decoding data signals read from magnetic tape, the magnetic tape including first reference signals recorded thereon at the beginning of the tape, the improvement comprising: a multi-stage amplifier for receiving said first reference signals and said data signals read from the tape for amplifying said signals, said amplifier being programmable to assume a plurality of different gains with each of the gains of the amplifier being related in a binary sequence KA n where K is an arbitrary constant, A is the gain of one amplifier stage and n is an integer including zero; means for decoding said amplified signals for deriving a decoded data signal, said decoding means including a source of second reference signals representing a voltage level of a predetermined magnitude greater than zero; first means for comparing the output of the amplifier to a reference voltage equal to zero and having an output when the amplitude of the amplifier signal exceeds said reference voltage; second means for comparing the output of the amplifier to said second reference signals and having an output when the amplified signal exceeds said second reference signals; a binary counter operated by said first reference signals to sequentially output a plurality of increasing binary numbers; switch means coupled to the output of said binary counter for incrementally increasing the gain of the amplifier in accordance with the output of said binary counter; feedback means for coupling the output of said second comparing means to said binary counter for inhibiting the incrementing of said counter whereby the gain of the amplifier is set at a level equal to the output of the binary counter; and gating means responsive to the outputs of said first and second comparing means for gating said decoded data signals from said first comparing means through said gating means when said second comparing means has an output in coincidence therewith.

Claim 9

A data decoding system in accordance with claim 6 wherein A is a number between one and two and n is an integer from zero through fifteen.

Claim 10

A data decoding system in accordance with claim 6 wherein each amplifier stage has a gain of either one or A n .

Claim 11

A data decoding system in accordance with claim 6 wherein: said second reference voltages comprise a plurality of signal clipping levels in accordance with the type of operation of said data decoding system; and means is provided for selectively coupling said clipping level voltages to said second comparator.

Claim 12

A data decoding system in accordance with claim 6 wherein said counter comprises a sixteen bit binary counter for incrementally increasing the total amplifier gain from (A) o to (A) 15 in sixteen binary steps.

Claim 13

A data decoding system in accordance with claim 10 wherein said amplifier comprises at least four stages, each stage being a transistor amplifier and wherein the gain of the first and second stages is determined by the ratio of the collector to emitter resistance and the gain of the third and fourth stages is determined by the ratio of the emitter to collector resistance, said switches are connected to a resistance in each stage to decrease the collector resistance in said first and second stages and the emitter resistance in said third and fourth stages when operated to sequentially and incrementally increase the total amplifier gain by said binary steps.

Claim 14

A data decoding system in accordance with claim 11 wherein the gain of said first stage is switchable between A o and A 1 , the gain of said second stage is switchable between A o and A 2 , the gain of said third stage is switchable between A o and A 4 , and the gain of said fourth stage is switchable between A o and A 8 .

Claim 15

In a system for decoding data signals read from a multi-channel magnetic tape wherein each channel has recorded therein a first reference signal located at the start of the channel, the improvement comprising: a four stage amplifier for amplifying the first reference signal read from one of the channels of the magnetic tape, each stage having a gain of either one or A n where A is a number greater than one and n is an integer equal to or greater than zero and wherein the first stage has a gain of either A o and A 1 , the second stage has a gain of either A o and A 2 , the third stage has a gain or either A o and A 4 , and the fourth stage has a gain of either A o and A 8 , and said amplifier having an output signal whose gain is equal to the product of the gain of each of the four stages of the amplifier; a plurality of switches each coupled to one of said stages of the amplifier for changing the gain of its associated stage from 1 to A n when operated; a plurality of four-bit binary counters, each coupled to the one channel of the magnetic tape and operated by said first reference signal recorded on that channel to incrementally output a predetermined number of increasing binary numbers; multiplexing means coupled to said switches and receiving the output of said binary counters to selectively operate said switches in accordance with the binary output of said counters wherein the gain of each amplifier stage is sequentially incremented through a number of increments corresponding to the binary number counted by said counters; a source of second reference signals representing a voltage level of a predetermined magnitude greater than zero; first means for comparing the output of the amplifier to a reference voltage equal to zero and having an output when the amplified signal exceeds said reference voltage; second means for comparing the output of the amplifier to said second reference signals and having an output when the amplified signal exceeds said second reference signals; feedback means for coupling the output of said second comparing means to said binary counters for inhibiting the incrementing of said counters whereby the gain of the amplifier is set at a level equal to the output of the binary counter; and gating means responsive to the output of said first and second comparing means for gating decoded data signals read from the one channel of the magnetic tape from said first comparing means through said gating means when said second comparing means has an output in coincidence therewith.

Claim 16

In a system for decoding data signals read from a multi-channel magnetic tape wherein each channel has recorded therein a first reference signal located at the start of the channel, the improvement comprising: a four stage amplifier for amplifying the first reference signal read from one of the channels of the magnetic tape, each stage having a gain of either one or A n where A is a number greater than one and n is an integer equal to or greater than zero and wherein the first stage has a gain of either A o and A 1 , the second stage has a gain of either A o and A 2 , the third stage has a gain or either A o and A 4 , and the fourth stage has a gain of either A o and A 8 , and said amplifier having an output signal whose gain is equal to the product of the gain of each of the four stages of the amplifier; a plurality of switches each coupled to one of said stages of the amplifier for changing the gain of its associated stage from 1 to A n when operated; a plurality of four-bit binary counters, each coupled to the one channel of the magnetic tape and operated by said first reference signal recorded on that channel to incrementally output a predetermined number of increasing binary numbers; multiplexing means coupled to said switches and receiving the output of said binary counters to selectively operate said switches in accordance with the binary output of said counters wherein the gain of each amplifier stage is sequentially incremented through a number of increments corresponding to the binary number counted by said counters; a source of second reference signals representing a voltage level of a predetermined magnitude greater than zero; first means for comparing the output of the amplifier to a reference voltage equal to zero and having an output when the amplified signal exceeds said reference voltage; second means for comparing the output of the amplifier to said second reference signals and having an output when the amplified signal exceeds said second reference signals; feedback means for coupling the output of said second comparing means to said binary counters for inhibiting the incrementing of said counters whereby the gain of the amplifier is set at a level equal to the output of the binary counter; and gating means responsive to the output of said first and second comparing means for gating decoded data signals read from the one channel of the magnetic tape from said first comparing means through said gating means when said second comparing means has an output in coincidence therewith.

Claim 17

A data decoding system in accordance with claim 13 wherein each amplifier stage is a transistor amplifier and wherein the gain of the first and second stages is determined by the ratio of the collector to emitter resistance and the gain of the third and fourth stages is determined by the ratio of the emitter to collector resistance, said switches are connected to a resistance in each stage to decrease the collector resistance in said first and second stages and the emitter resistance in said third and fourth stage when operated to sequentially and incrementally increase the total amplifier gain by said binary steps.

Claim 18

A programmable amplifier having a gain variable in incremental binary steps comprising: a four stage transistor amplifier for amplifying a data signal, each stage having a gain of either one or A n where A is a number greater than one less than two and n is an integer equal to or greater than zero but less than sixteen, said stages having an output signal whose gain is equal to the product of the gain of each stage of amplification wherein the gain of the first and second stages is determined by the ratio of the collector to emitter resistance and the gain of the third and fourth stages is determined by the ratio of the emitter to collector resistance; a source of first reference signals for inputting into the said stages of amplification; a binary counter operated by said first reference signals to incrementally output a predetermined number of increasing binary numbers, said counter comprising a sixteen bit binary counter incrementally increasing the total amplifier gain from (A) o to (A) 15 in sixteen binary steps; a plurality of switches corresponding in number to the number of amplifier stages with each of said switches being associated with a respective stage of amplification and coupled to each of said amplifier stages for incrementally changing the gain of each stage from one to A n when operated, said switches being connected to a resistance in each stage to decrease the collector resistance in said first and second stages and the emitter resistance in said third and fourth stages when operated to sequentially and incrementally increase the total amplifier gain by said binary steps; decoding means coupled to said switches and said binary counter for receiving the binary output of said counter to operate said switches in accordance with the binary output of said counter wherein the amplifier gain is sequentially incremented through a number of increments corresponding to said predetermined number counted by said counter; a source of second reference signals; and means for comparing the output signal of said transistor stages derived from said first reference signals with said second reference signals and responsive to said output signal being equal to or exceeding said second reference signal for inhibiting the incrementing of said binary counter.

Claim 19

A programmable amplifier having a gain variable in incremental binary steps comprising: a four stage transistor amplifier for amplifying a data signal, each stage having a gain of either one or A n where A is a number greater than one less than two and n is an integer equal to or greater than zero but less than sixteen, said stages having an output signal whose gain is equal to the product of the gain of each stage of amplification wherein the gain of the first and second stages is determined by the ratio of the collector to emitter resistance and the gain of the third and fourth stages is determined by the ratio of the emitter to collector resistance; a source of first reference signals for inputting into the said stages of amplification; a binary counter operated by said first reference signals to incrementally output a predetermined number of increasing binary numbers, said counter comprising a sixteen bit binary counter incrementally increasing the total amplifier gain from (A) o to (A) 15 in sixteen binary steps; a plurality of switches corresponding in number to the number of amplifier stages with each of said switches being associated with a respective stage of amplification and coupled to each of said amplifier stages for incrementally changing the gain of each stage from one to A n when operated, said switches being connected to a resistance in each stage to decrease the collector resistance in said first and second stages and the emitter resistance in said third and fourth stages when operated to sequentially and incrementally increase the total amplifier gain by said binary steps; decoding means coupled to said switches and said binary counter for receiving the binary output of said counter to operate said switches in accordance with the binary output of said counter wherein the amplifier gain is sequentially incremented through a number of increments corresponding to said predetermined number counted by said counter; a source of second reference signals; and means for comparing the output signal of said transistor stages derived from said first reference signals with said second reference signals and responsive to said output signal being equal to or exceeding said second reference signal for inhibiting the incrementing of said binary counter.

Claim 20

A programmable amplifier in accordance with claim 15 wherein the gain of said first stage is switchable between A o and A 1 , the gain of said second stage is switchable between A o and A 2 , the gain of said third stage is switchable between A o and A 4 , and the gain of said fourth stage is switchable between A o and A 8 .