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US3579138A
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Automatic gain presetting circuit
Assignee: American Optical Corp
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Filing: 1969-08-25
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Granted: 1971-05-18
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Expires: 1989-08-25
Abstract
Abstract An automatic gain presetting circuit for adjusting the gain of an operational amplifier. A full-wave rectifier and peak detector determine the peak input. A counter is incremented continuously and a reference voltage is developed which increases with the increasing count. The reference voltage is compared with the detected peak voltage and when the reference voltage is equal to or greater than the peak input voltage the counter ceases to increment. A plurality of resistors are connectable in parallel in the feedback path of the operational amplifier, but each individual resistor is connected in the feedback path only if a respective stage in the counter is in a predetermined state. The gain of the operational amplifier depends upon the total effective feedback impedance. The larger the final count in the counter, corresponding to a larger peak input signal, the smaller the total effective feedback impedance and the lower the gain of the amplifier.
Inventors
- 👤 George J Harris
- 👤 Christopher C Day
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:06
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; A; A61; A61B; A61B5/00; A61B5/24; A61B5/30; A61B5/307; A61B5/308; Y; Y10; Y10S; Y10S128/00; Y10S128/902
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
96 words
An automatic gain presetting circuit for an amplifier comprising means for deriving a signal dependent upon the peak amplitude of an input signal, a counter, means for succeSsively incrementing said counter, means responsive to the successive incrementing of said counter and not to said amplifier for deriving a continuously increasing reference signal, means for comparing said reference signal with said derived signal and responsive to said reference signal exceeding said derived signal for inhibiting the incrementing of said counter, and means dependent upon the count stored in said counter for controlling the gain of said amplifier.
Claim 2
Dependent Claim
96 words
An automatic gain presetting circuit for an amplifier comprising means for deriving a signal dependent upon the peak amplitude of an input signal, a counter, means for succeSsively incrementing said counter, means responsive to the successive incrementing of said counter and not to said amplifier for deriving a continuously increasing reference signal, means for comparing said reference signal with said derived signal and responsive to said reference signal exceeding said derived signal for inhibiting the incrementing of said counter, and means dependent upon the count stored in said counter for controlling the gain of said amplifier.
Claim 3
Dependent Claim
55 words
An automatic gain presetting circuit in accordance with claim 1, wherein said amplifier is an operational amplifier including a plurality of feedback resistors selectively connectable therein, and said gain controlling means controls the connection of respective resistors in the feedback path of said amplifier dependent upon the values of respective bits represented in said counter.
Claim 4
Dependent Claim
61 words
An automatic gain presetting circuit in accordance with claim 2 wherein said counter includes a plurality of flip-flop stages and said reference signal deriving means includes a plurality of weighted resistors each connected at one end thereof to a respective one of said stages with all of said resistors being connected together at the other ends thereof to said comparing means.
Claim 5
Dependent Claim
77 words
An automatic gain presetting circuit in accordance with claim 3 wherein each of said flip-flop stages when in a selected state controls the connection of a respective one of said resistors in the feedback path of said amplifier, with all of the connected resistors being connected in parallel in said feedback path, and said feedback resistors have a sequence of magnitudes which correspond inversely to the order of significance of the respective bits represented in said counter.
Claim 6
Dependent Claim
42 words
An automatic gain presetting circuit in accordance with claim 4 wherein said signal deriving means includes a full-wave rectifier, peak detecting means, and means for averaging out input signal fluctuations during an initial monitoring period prior to the incrementing of said counter.
Claim 7
Dependent Claim
42 words
An automatic gain presetting circuit in accordance with claim 1 wherein said signal deriving means includes a full-wave rectifier, peak detecting means, and means for averaging out input signal fluctuations during an initial monitoring period prior to the incrementing of said counter.
Claim 8
Dependent Claim
109 words
An automatic gain presetting circuit for an amplifier comprising means for deriving a signal dependent upon the peak amplitude of an input signal, counting means, means for successively changing the count in said counting means in a predetermined direction, means responsive to successive changes in the count in said counting means and not to said amplifier for deriving a continuously changing reference signal, means for comparing said reference signal with said derived signal and responsive to a relative change in polarity for inhibiting changes in the count in said counting means, and means dependent upon the final count in said counting means for controlling the gain of said amplifier.
Claim 9
Dependent Claim
109 words
An automatic gain presetting circuit for an amplifier comprising means for deriving a signal dependent upon the peak amplitude of an input signal, counting means, means for successively changing the count in said counting means in a predetermined direction, means responsive to successive changes in the count in said counting means and not to said amplifier for deriving a continuously changing reference signal, means for comparing said reference signal with said derived signal and responsive to a relative change in polarity for inhibiting changes in the count in said counting means, and means dependent upon the final count in said counting means for controlling the gain of said amplifier.
Claim 10
Dependent Claim
47 words
An automatic gain presetting circuit in accordance with claim 7 wherein said gain controlling means is operative to decrease the gain of said amplifier in direct proportion to the total change in the count in said counting means prior to the inhibiting of changes in said count.
Claim 11
Dependent Claim
68 words
An automatic gain presetting circuit in accordance with claim 8 wherein said amplifier includes a plurality of feedback resistors selectively connectable in parallel therein, said counting means includes a plurality of flip-flop stages, and said gain controlling means includes means for connecting each of said feedback resistors in the feedback path of said amplifier responsive to a respective one of said flip-flop stages being in a predetermined state.
Claim 12
Dependent Claim
56 words
An automatic gain presetting circuit in accordance with claim 9 wherein said reference signal deriving means includes a plurality of reference means resistors each connected at one end thereof to a respective one of said flip-flop stages with all of said reference meaNs resistors being connected together at the other ends thereof to said comparing means.
Claim 13
Dependent Claim
37 words
An automatic gain presetting circuit in accordance with claim 10 wherein the magnitudes of each of said plurality of feedback resistors and said plurality of reference means resistors are related to each other in a binary sequence.
Claim 14
Dependent Claim
45 words
An automatic gain presetting circuit in accordance with claim 11 wherein said signal deriving means includes a full-wave rectifier, peak detecting means, and means for averaging out input signal fluctuations during an initial monitoring period prior to the changing of the count in said counter.
Claim 15
Dependent Claim
45 words
An automatic gain presetting circuit in accordance with claim 7 wherein said signal deriving means includes a full-wave rectifier, peak detecting means, and means for averaging out input signal fluctuations during an initial monitoring period prior to the changing of the count in said counter.
References Cited (Backward Citations)
US3376557A
Cited
US3378786A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |