Synchronization for PCM transmission systems

Claim 2

A pulse code modulation (PCM) system comprising: a transmitter including an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit information in a line code signal having a given bit rate; and a receiver including second means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; third means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said second and third means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said second means to produce an output signal dependent on the relationship between said line code signal and said derived clock; bistable means coupled to said second gating means responsive to said output signal to recreate said binary bits of said PCM signal at said input.

Claim 3

A system according to claim 1, wherein said information transmitted by said position modulation of said one of said line code transition is synchronization information.

Claim 4

A system according to claim 2, wherein said first means includes an N-stage distributor coupled to said input, where N is an integer greater than one; fourth means coupled to said distributor for selecting the outputs of said distributor to provide line code bits having normal transition positions with respect to a period of said line code bits and the outputs of said distributor to provide said line code bits each having said position modulation of at least one transition with respect to the normal time of occurrence of said one transition, and clock means operating at N times said given bit rate coupled to said distributor to control said distributor.

Claim 5

A system according to claim 2, wherein said first means includes a D-type flip flop having a data input coupled to said input for said PCM signal and a clock input receiving a modulated clock pulse having a bit rate equal to the bit rate of said PCM signal.

Claim 6

A system according to claim 4, wherein said modulated clock pulse is phase modulated.

Claim 7

A system according to claim 4, wherein said modulated clock pulse is pulse width modulated.

Claim 8

A pulse code modulation (PCM) system comprising: a transmitter including input means for binary bits of a PCM signal; and N-stage distributor means coupled to said input means for introducing a position modulation of at least one of said binary bits without the addition of additional bits to said PCM signal to transmit an information signal having a given bit rate, where N is greater than one; and a receiver including a phase locked loop having a phase comparator coupled to said distributor means, a low pass filter coupled to the output of said phase comparator, and a voltage controlled oscillator having its input coupled to the output of said filter and its output coupled to said phase comparator as a second input thereto; said position modulation being produced at the output of said phase comparator.

Claim 9

A pulse code modulation (PCM) system comprising: a transmitter including input means for binary bits of a PCM signal; and N-stage distributor means coupled to said input means for introducing a position modulation of at least one of said binary bits without the addition of additional bits to said PCM signal to transmit an information signal having a given bit rate, where N is greater than one; and a receiver including a phase locked loop having a phase comparator coupled to said distributor means, a low pass filter coupled to the output of said phase comparator, and a voltage controlled oscillator having its input coupled to the output of said filter and its output coupled to said phase comparator as a second input thereto; said position modulation being produced at the output of said phase comparator.

Claim 10

A system according to claim 7, wherein said information transmitted by said position modulation of said one of said binary bits is synchronization information.

Claim 11

A pulse code modulation (PCM) transmitter comprising: an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit synchronization information in a line code signal, wherein; said first means includes an N-stage distributor coupled to said input, where N is an integer greater than one, second means coupled to said distributor for selecting the outputs of said distributor to provide line code bits having normal transition positions with respect to a period of said line code bits and the outputs of said distributor to provide said line code bits each having said position modulation of at least one transition with respect to the normal time of occurrence of said one transition, such that additional bits are not added to said line code, and clock means operating at N times said given bit rate coupled to said distributor to control said distributor.

Claim 12

A pulse code modulation (PCM) transmitter comprising: an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit synchronization information in a line code signal, wherein; said first means includes an N-stage distributor coupled to said input, where N is an integer greater than one, second means coupled to said distributor for selecting the outputs of said distributor to provide line code bits having normal transition positions with respect to a period of said line code bits and the outputs of said distributor to provide said line code bits each having said position modulation of at least one transition with respect to the normal time of occurrence of said one transition, such that additional bits are not added to said line code, and clock means operating at N times said given bit rate coupled to said distributor to control said distributor.

Claim 13

A transmitter according to claim 9 wherein said first means includes a D-type flip flop having a data input coupled to said input for said PCM signal and a clock input receiving a modulated clock pulse having a bit rate equal to the bit rate of said PCM signal.

Claim 14

A transmitter according to claim 10, wherein said modulated clock pulse is phase modulated.

Claim 15

A transmitter according to claim 10, wherein said modulated clock pulse is pulse width modulated.

Claim 16

A pulse code modulation (PCM) receiver for a line code signal having at least one line code transition position modulated to convey information in a line code signal having a given bit rate comprising: first means to receive said line code signal; second means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; third means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said second and third means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said second means to produce an output signal dependent on the relationship between said line code signal and said derived clock; bistable means coupled to said second gating means responsive to said output signal to recreate binary bits of an original PCM signal at a transmitter.

Claim 17

A pulse code modulation (PCM) receiver for a line code signal having at least one line code transition position modulated to convey information in a line code signal having a given bit rate comprising: first means to receive said line code signal; second means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; third means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said second and third means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said second means to produce an output signal dependent on the relationship between said line code signal and said derived clock; bistable means coupled to said second gating means responsive to said output signal to recreate binary bits of an original PCM signal at a transmitter.

Claim 18

A receiver according to claim 13, wherein said information transmitted by said position modulation of said one of said line code transition is synchronization information.

Claim 19

A pulse code modulation (PCM) system comprising: a transmitter including an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit synchronization information in a line code signal having a given bit rate; and a receiver including second means coupled to said first means for demodulating said line code transition position modulation; wherein said first means includes an N-Stage distrubutor coupled to said input, where N is equal to an integer greater than one. third means coupled to said distributor for selecting the outputs of said distributor to provide line code bits having normal transition positions with respect to a period of said line code bits and the outputs of said distributor to provide said line code bits each having said position modulation of at least one transition with respect to the normal time of occurrence of said one transition, such that additional bits are not added to said line code and clock means operating at N times said given bit rate coupled to said distributor to control said distributor.

Claim 20

A pulse code modulation (PCM) system comprising: a transmitter including an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit synchronization information in a line code signal having a given bit rate; and a receiver including second means coupled to said first means for demodulating said line code transition position modulation; wherein said first means includes an N-Stage distrubutor coupled to said input, where N is equal to an integer greater than one. third means coupled to said distributor for selecting the outputs of said distributor to provide line code bits having normal transition positions with respect to a period of said line code bits and the outputs of said distributor to provide said line code bits each having said position modulation of at least one transition with respect to the normal time of occurrence of said one transition, such that additional bits are not added to said line code and clock means operating at N times said given bit rate coupled to said distributor to control said distributor.

Claim 21

A system according to claim 15 wherein said first means includes a D-type flip flop having a data input coupled to said input for said PCM signal and a clock input receiving a modulated clock pulse having a bit rate equal to the bit rate of said PCM signal.

Claim 22

A system according to claim 16, wherein said modulated clock pulse is phase modulated.

Claim 23

A system according to claim 16, wherein said modulated clock pulse is pulse width modulated.

Claim 24

A pulse code modulation (PCM) system comprising: a transmitter including an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit synchronization information in a line code signal having a given bit rate; and a receiver including second means coupled to said first means for demodulating said line code transition position modulation, said second means including: a third means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; fourth means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said third and fourth means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said third means to produce an output signal dependent upon the relationship between said line code signal and said derived clock; and bistable means coupled to said second gating means responsive to said output signal to recreate said binary bits of said PCM signal at said input.

Claim 25

A pulse code modulation (PCM) system comprising: a transmitter including an input for binary bits of a PCM signal; and first means coupled to said input for introducing a position modulation of at least one line code transition to transmit synchronization information in a line code signal having a given bit rate; and a receiver including second means coupled to said first means for demodulating said line code transition position modulation, said second means including: a third means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; fourth means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said third and fourth means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said third means to produce an output signal dependent upon the relationship between said line code signal and said derived clock; and bistable means coupled to said second gating means responsive to said output signal to recreate said binary bits of said PCM signal at said input.

Claim 26

A pulse code modulation (PCM) receiver for a line code signal having at least one line code transition position modulated to convey synchronization information in a line code signal having a given bit rate comprising: first means to receive said line code signal; and second means coupled to said first means for demodulating said line code transition position modulation, said second means including: a third means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; fourth means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said third and fourth means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said third means to produce an output signal dependent upon the relationship between said line code signal and said derived clock; and bistable means coupled to said second gating means responsive to said output signal to recreate said binary bits of said PCM signal at said input.

Claim 27

A pulse code modulation (PCM) receiver for a line code signal having at least one line code transition position modulated to convey synchronization information in a line code signal having a given bit rate comprising: first means to receive said line code signal; and second means coupled to said first means for demodulating said line code transition position modulation, said second means including: a third means coupled to said first means to derive from said line code signal a clock having a specified relationship to said given bit rate; fourth means coupled to said first means to full wave rectify said line code signal; first gating means coupled to said third and fourth means responsive to said derived clock and said rectified signal to recreate said line code transition position modulation; second gating means coupled to said first means and said third means to produce an output signal dependent upon the relationship between said line code signal and said derived clock; and bistable means coupled to said second gating means responsive to said output signal to recreate said binary bits of said PCM signal at said input.