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US4084069A Expired / Lapsed US ⏱️ 0.0 years remaining

Encoding and driving means for use in a three-level digital data communication system

Assignee: Unisys Corp
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Filing: 1976-11-01
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Granted: 1978-04-11
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Expires: 1996-11-01
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Abstract

Abstract Improved encoding and driving means for use in a direct-coupled, three-level binary serial digital data transmission channel. The binary data to be transmitted is encoded into a three-level signal requiring only one transition per bit. A three-state balanced direct-coupled differential driving circuit comprised of dual differential amplifiers is used for driving the transmission line.

Inventors

  • 👤 Floyd William Looschen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 06:25
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 141 words
For use in a three-level digital data transmission line driving system, the combination comprising: means for providing high and low binary signals H and L indicative of high and low levels of a three-level signal, and a three-state balanced differential driving circuit to which said H and L signals are applied, said driving circuit including a pair of dual differential drivers having inputs responsive to said H and L signals and outputs coupled to a pair of output lines for providing driving thereof by a three-level signal having levels responsive to said H and L signals, said dual differential drivers being responsive to said H and L signals so as to provide across said pair of output lines a three-level signal whose levels are represented by the following: (1) a high signal, (2) a low signal, and (3) a high impedance.
Claim 2
Dependent Claim 141 words
For use in a three-level digital data transmission line driving system, the combination comprising: means for providing high and low binary signals H and L indicative of high and low levels of a three-level signal, and a three-state balanced differential driving circuit to which said H and L signals are applied, said driving circuit including a pair of dual differential drivers having inputs responsive to said H and L signals and outputs coupled to a pair of output lines for providing driving thereof by a three-level signal having levels responsive to said H and L signals, said dual differential drivers being responsive to said H and L signals so as to provide across said pair of output lines a three-level signal whose levels are represented by the following: (1) a high signal, (2) a low signal, and (3) a high impedance.
Claim 3
Dependent Claim 172 words
The invention in accordance with claim 1, wherein each dual differential driver comprises: means responsive to a respective one of said H and L signals for producing opposite binary signals corresponding thereto: a first amplifier providing first and second outputs and having an input connected to receive one of said opposite binary signals; a second amplifier providing first and second outputs and having an input connected to receive the other of said opposite binary signals; each amplifier being operative in response to the binary signal applied to its input such that one value of the binary signal applied thereto results in producing a high voltage level on its first output and a high impedance on its second output, and the other value of the binary signal applied thereto results in producing a low voltage level on its second output and a high impedance on its first output, and means coupling respective ones of the outputs of said amplifiers to respective ones of said pair of output lines for providing said three-level signal.
Claim 4
Dependent Claim 154 words
The invention in accordance with claim 2, wherein said H signal is applied to a first one of said dual differential drivers and said L signal is applied to a second one of said dual differential drivers; wherein H and H are respectively applied to the inputs of the first and second amplifiers of said differential driver and L and L are respectively applied to the inputs of the first and second amplifiers of said second differential driver; wherein the first output of the first amplifier of said first differential driver and the second output of the second amplifier of said second differential driver are both coupled to one of said pair of output lines; and wherein the second output of the second amplifier of said first differential driver and the first output of the first amplifier of said second differential driver are both coupled to the other of said pair of output lines.
Claim 5
Dependent Claim 98 words
The invention in accordance with claim 3, wherein said means for providing said high and low binary signals H and L includes encoding means responsive to an input binary signal for producing signals H and L in accordance with the following Boolean equations: H = B H.sub.p L.sub.p + B H.sub.p L.sub.p L = B H.sub.p L.sub.p + B H.sub.p L.sub.p wherein B and B respectively correspond to the two binary digits of said binary input signal and H p , H p , L p and L p are representative of previous values of H and L.

References Cited (Backward Citations)

US3980826A Cited
US3993953A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-04-10 1981-10-10 1982-04-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-04-10 1985-10-10 1986-04-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-04-10 1989-10-10 1990-04-11 $7700.00 Window Closed / Lapsed

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