Current mode 4-bit arithmetic logic unit with parity

Claim 1

A current mode 4-bit arithmetic logic unit for performing a repertoire of binary arithmetic and logic operations on two n-bit plus parity input bytes Ai and Bi, where O< n≦4, said arithmetic logic unit further performing parity prediction, parity checking, and carry checking operations, said arithmetic logic unit comprising: a first portion for receiving said first and second n-bit bytes Ai and Bi, a carry-in signal CIN, a mode control signal, and generating a binary output resultant signal Fi in response to said mode control signal; and a second portion receiving said carry-in signal CIN, a carry-in duplicate signal CIND, and the parity bits AP and BP associated with said first and second n-bit bytes, said second portion further receiving as inputs thereto a carry error signal CE, a parity of the half-sums signal HS, a parity of the half parities signal HP, an invert parity signal IP, a parity check signal PCK, a pair of configuration select signals P1 and P2, and a parity of the carries signal PC from an external source, said second portion generating a parity prediction signal FP and error signal E in accordance with the following logic equations: Parity (FP) and Error (E) Outputs: FP = }CIN·[HS1·K2) + (HS2·K4·(HS4·K8))]·M16} ⊕ {g1·k2·[(hs2·k4) + (hs4·k8)]·M16} ⊕ {g2·k4·(hs4·k8)·m16} ⊕ {g4·k8·m16} ⊕ {ip} ⊕ {pc} ⊕ {hs ⊕ hs1 ⊕ (hs2·k2) ⊕ (hs4·k4) ⊕ (hs8·k8)} e = {(cin ⊕ cin)·m16} + {ce} + }[ap ⊕ bp} ⊕ [hs ⊕ hs1 ⊕ (hs2·k2) ⊕ (hs4·k4) ⊕ (hs8·k8)] ⊕ [hp ⊕ hp1 ⊕ (hp2·k2) ⊕ (hp4·k4) ⊕ (hp8·k8)] ·pck k2 = p2 + p1 k4 = p2 k8 = p2·p1 half Sum, Half Parity, Propagates, and Generates Intermediate Signals (HSi, HPi, Pi, PPi, Gi, GPi): ______________________________________ Half Sum, Half Parity, Propagates, and Generates Intermediates Signals (HSi, HPi, Pi, PPi, Gi, GPi): For i = 1,2,4,8 Gi = M8·Ai·Bi + N4·Ai·--Bi GPi = M8·Bi·Ai + M1·Bi.multid ot.--Ai Pi = Ai + M2·--Bi +M1·Bi PPi = Bi + M2·--Ai + M4·Ai HSi = --Gi·Pi HPi = ----GPi·PPi M8 M4 M2 M1 HSi HPi ______________________________________ 0 0 0 0 Ai Bi 0 0 0 1 Ai + Bi Ai·Bi 0 0 1 0 Ai + --Bi --Ai + Bi 0 0 1 1 1 Ai --⊕ Bi 0 1 0 0 Ai·Bi Ai + Bi 0 1 0 1 Bi Ai 0 1 1 0 Ai --⊕ Bi 1 0 1 1 1 --Ai + Bi Ai + --Bi 1 0 0 0 Ai·--Bi --Ai·Bi 1 0 0 1 Ai ⊕ Bi 0 1 0 1 0 --Bi --Ai 1 0 1 1 --Ai + --Bi --Ai ·--Bi 1 1 0 0 0 Ai ⊕ Bi 1 1 0 1 --Ai·Bi Ai·--Bi 1 1 1 0 --Ai ·--Bi --Ai + --Bi 1 1 1 1 --Ai --Bi Carry Intermediate Signals (Ci): C1 = CIN C2 = G1 + HS1·CIN C4 = G2 + HS2·G1 + HS2·HS1·CIN C8 = G4 + HS4·G2 + HS4·HS2·G1 + HS4·HS2·HS1·CIN . # of Active P2 P1 K8 K4 K2 Bits n in ALU ______________________________________ 0 0 0 0 0 1 0 1 0 0 1 2 1 0 0 1 1 3 1 1 1 1 1 4 ______________________________________