Patent US3705003A successfully refreshed from Google Patents.
Patent US4081292A successfully refreshed from Google Patents.
US4081292A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semi-insulating silicon layer
Assignee: Sony Corp
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Filing: 1976-04-19
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Granted: 1978-03-28
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Expires: 1996-04-19
Abstract
Abstract Silicon ions are implanted in a silicon dioxide layer on a silicon substrate so that the dioxide layer is converted into a semi-insulating layer having an improved passivation property.
Inventors
- 👤 Teruaki Aoki
- 👤 Takeshi Matsushita
- 👤 Tadayoshi Mifune
- 👤 Motoaki Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:11
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W74/00; H10W74/40; H10W74/43
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
96 words
The method of manufacturing an element which includes forming a silicon compound layer on a silicon substrate, the silicon compound layer initially being an insulator, implanting silicon ions by a silicon ion beam into said compound layer and into a portion of said substrate on the side of its interface with said compound layer, said compound layer being converted thereby into a semi-insulating layer, said portion of said substrate being converted into an amorphous silicon portion, annealing said substrate, whereby said portion is reconverted to form a single crystal with the remaining portion of said substrate.
Claim 2
Independent Claim
96 words
The method of manufacturing an element which includes forming a silicon compound layer on a silicon substrate, the silicon compound layer initially being an insulator, implanting silicon ions by a silicon ion beam into said compound layer and into a portion of said substrate on the side of its interface with said compound layer, said compound layer being converted thereby into a semi-insulating layer, said portion of said substrate being converted into an amorphous silicon portion, annealing said substrate, whereby said portion is reconverted to form a single crystal with the remaining portion of said substrate.
Claim 3
Dependent Claim
15 words
A method according to claim 1, in which said compound layer is SiO 2 .
Claim 4
Dependent Claim
59 words
A method according to claim 2, in which a silicon ion beam implants silicon ions into said silicon dioxide layer, the energy of said silicon ion beam being selected sufficient to convert the silicon dioxide layer into a polycrystalline silicon layer having a concentration of 2 to 45 atomic percent of oxygen at the bottom of the insulating layer.
Claim 5
Dependent Claim
59 words
A method according to claim 2, in which a silicon ion beam implants silicon ions into said silicon dioxide layer, the energy of said silicon ion beam being selected sufficient to convert the silicon dioxide layer into a polycrystalline silicon layer having a concentration of 15 to 35 atomic percent of oxygen at the bottom of the insulating layer.
Claim 6
Dependent Claim
17 words
A method according to claim 1, in which said compound layer is Si 3 N 4 .
Claim 7
Dependent Claim
57 words
A method according to claim 3, in which a silicon ion beam implants silicon ions into said silicon nitride layer, the energy of said silicon ion beam being selected sufficient to convert the silicon nitride layer into a polycrystalline silicon layer having a concentration above 10 atomic percent of nitrogen at the bottom of the insulating layer.
Claim 8
Independent Claim
42 words
A method of manufacturing a semiconductor device which includes forming a silicon compound layer on a semiconductor substrate, subjecting said layer to a silicon ion beam to implant silicon ions in said layer, and then converting said layer into a semi-insulating layer.
Claim 9
Independent Claim
42 words
A method of manufacturing a semiconductor device which includes forming a silicon compound layer on a semiconductor substrate, subjecting said layer to a silicon ion beam to implant silicon ions in said layer, and then converting said layer into a semi-insulating layer.
Claim 10
Independent Claim
207 words
The method of manufacturing a bipolar junction transistor device which includes forming a silicon dioxide mask on one planar face of a single crystal semiconductor substrate of a first conductivity type to provide a collector region by selectively etching said mask, causing a base region of the opposite conductivity type to be diffused into said one planar surface to provide a base region, causing an emitter region of said first conductivity type to be diffused into the planar face of said base region, reducing the thickness of said SiO 2 layer over a portion of said base region and over the surface region of the emitter-base junction, reducing the SiO 2 layer over said emitter region which lies radially inwardly of said emitter-base junction, subjecting the side of said device which contains said base and said emitter to a silicon ion beam having a mean depth of ion penetration which approximately equals the original thickness of said SiO 2 layer, whereby the lower portion of said SiO 2 layer is converted into a polycrystalline silicon layer and the upper portion of said substrate is converted into an amorphous layer, annealing said substrate, whereby said amorphous layer is converted back into a single crystal portion of said substrate.
Claim 11
Independent Claim
207 words
The method of manufacturing a bipolar junction transistor device which includes forming a silicon dioxide mask on one planar face of a single crystal semiconductor substrate of a first conductivity type to provide a collector region by selectively etching said mask, causing a base region of the opposite conductivity type to be diffused into said one planar surface to provide a base region, causing an emitter region of said first conductivity type to be diffused into the planar face of said base region, reducing the thickness of said SiO 2 layer over a portion of said base region and over the surface region of the emitter-base junction, reducing the SiO 2 layer over said emitter region which lies radially inwardly of said emitter-base junction, subjecting the side of said device which contains said base and said emitter to a silicon ion beam having a mean depth of ion penetration which approximately equals the original thickness of said SiO 2 layer, whereby the lower portion of said SiO 2 layer is converted into a polycrystalline silicon layer and the upper portion of said substrate is converted into an amorphous layer, annealing said substrate, whereby said amorphous layer is converted back into a single crystal portion of said substrate.
Claim 12
Dependent Claim
29 words
The method of manufacturing a bipolar junction transistor device according to claim 8, in which the temperature of the annealing step is at a temperature of over 500° C.
Claim 13
Dependent Claim
27 words
The method of manufacturing a bipolar junction transistor device according to claim 8, in which the accelerating energy of the silicon ion beam is approximately 200 KeV.
Claim 14
Dependent Claim
46 words
The method of manufacturing a bipolar junction transistor device according to claim 8, wherein the accelerating energy of the silicon ion beam is sufficient to convert the region of said SiO 2 layer above said collector region and above said base region into a polycrystalline region.
Claim 15
Dependent Claim
95 words
The method of manufacturing a bipolar junction transistor device according to claim 8, wherein an additional Si 3 N 4 layer is deposited on said SiO 2 layer before said substrate is subjected to a silicon ion beam, the combined thickness of said original SiO 2 layer and said Si 3 N 4 layer being approximately 0.22μ and wherein the dosing by said Si + ion beam is 1.6 × 10 18 cm -2 , whereby after said annealing step the Si 3 N 4 and the SiO 2 layers are converted into polycrystalline layers.
Claim 16
Independent Claim
135 words
A method of manufacturing a bipolar junction transistor having a substrate, a collector region formed in a planar surface of said substrate, a base region formed in the planar surface of said collector region and an emitter formed in the planar surface of said base region, forming a silicon dioxide layer on the surface of said substrate which at least covers the ends of the base-collector junction and the emitter-base junction, subjecting the silicon dioxide layer to a silicon ion beam to implant silicon ions in the silicon dioxide layer, the energy of the silicon ion beam being such as to cause the mean depth of penetration of silicon ions to be approximately equal to the depth of said silicon dioxide layer, and annealing said layer whereby said layer is converted into a semi-insulating layer.
Claim 17
Independent Claim
135 words
A method of manufacturing a bipolar junction transistor having a substrate, a collector region formed in a planar surface of said substrate, a base region formed in the planar surface of said collector region and an emitter formed in the planar surface of said base region, forming a silicon dioxide layer on the surface of said substrate which at least covers the ends of the base-collector junction and the emitter-base junction, subjecting the silicon dioxide layer to a silicon ion beam to implant silicon ions in the silicon dioxide layer, the energy of the silicon ion beam being such as to cause the mean depth of penetration of silicon ions to be approximately equal to the depth of said silicon dioxide layer, and annealing said layer whereby said layer is converted into a semi-insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-27 | 1981-09-26 | 1982-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-27 | 1985-09-26 | 1986-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-27 | 1989-09-26 | 1990-03-28 | $7700.00 | Window Closed / Lapsed |