Micro program control system

Claim 2

A micro program control system for use in a data processing system which effects data processing along with a sequence of macro instructions stored in a main memory by fetching these macro instructions one by one and storing in an instruction register, the micro program control system comprising: control register means for holding a micro instruction for supplying control signals to said data processing system wherein said control signals correspond to the contents of the micro instruction; subsidiary control memory, connected to said control register means, for storing the first micro instructions of respective micro programs; control memory means, connected to said control register means, for storing the second and the remaining micro instructions of the respective micro programs; first addressing means, connected to said control memory means, said instruction register and said control register means; said first addressing means responsive to the contents of said control register means, for successively addressing said control memory means to read out the second and the remaining micro instructions of a micro program corresponding to the macro instruction in the instruction register into said control register means; and second addressing means, connected between said main memory and said subsidiary control memory means for addressing said subsidiary conntrol memory to read out the first micro instruction into said control register means in response to the contents of the operation code of the macro instruction read out from said main memory.

Claim 3

A micro program control system as defined in claim 1, wherein said first addressing means comprises: address register means connected to said control memory means for holding the address of a micro instruction to be read out from the control memory means; address selector means connected to the address register means for updating the contents of the address register means; decoder means connected to said instruction register for decoding the operation code of the macro instruction held in said instruction register to supply first address information to said address selector means; means for incrementing the address value indicated by the address register means to supply second address information to said address selector means; means for supplying third address information represented by the micro instruction in said control register means to said address selector means; and said address selector means selecting an address signal from among the first, second and third address information provided thereto in response to the contents of the control register means, thereby to supply the address to said address register means.

Claim 4

A micro program control system as defined in claim 2, wherein the operation code of the macro instruction includes a first operation code field for indicating the type of micro instruction format, and a second operation code field for indicating the type of operation in the data processing system, with the macro instruction being fetched from said main memory and stored in said instruction register, said second addressing means being coupled with a portion of said data lines, through which the first operation code field of the macro instruction is transferred, thereby addressing the first micro instruction corresponding to the contents of the first operation code field of the macro instruction.

Claim 5

A micro program control system for use in a data processing system which effects data processing along with a sequence of macro instructions stored in a main memory by fetching these macro instructions one by one and storing in an instruction register, the micro program control system comprising: control register means for holding a micro instruction for supplying control signals to said data processing system wherein said control signals correspond to the contents of the micro instruction; subsidiary control memory means connected to the control register for storing the first micro instructions of the respective micro programs, one of the micro instructions having a particular bit pattern which comprises zero value bits for the most part and unique value bits for the remaining part, and the bit pattern of the first micro instructions omitting such bits that correspond to the unique value bits of the micro instruction in a control memory means; said control memory means connected to said control register for storing the second and remaining micro instructions of respective micro programs; first adddressing means connected to said control memory means, said instruction means and said control register means, responsive to the contents of said instruction register and to the contents of said control register means for successively addressing said control memory means to read out one of the micro instructions of a micro program, corresponding to the macro instruction in the instruction register, into said control register means, said first addressing means supplying the micro instruction having the particular bit pattern to said control register means in synchronism with the reading out of the macro instruction from the main memory; and second addressing means connected between said main memory and said subsidiary control memory means for addressing said subsidiary control memory means to read out the first micro instruction into said control register means in response to the contents of the operation code of the macro instruction read out from the main memory.

Claim 6

A micro program control system for use in a data processing system which effects data processing along with a sequence of macro instructions stored in a main memory by fetching these macro instructions one by one and storing in an instruction register, the micro program control system comprising: control register means for holding a micro instruction for supplying control signals to said data processing system wherein said control signals correspond to the contents of the micro instruction; subsidiary control memory means connected to the control register for storing the first micro instructions of the respective micro programs, one of the micro instructions having a particular bit pattern which comprises zero value bits for the most part and unique value bits for the remaining part, and the bit pattern of the first micro instructions omitting such bits that correspond to the unique value bits of the micro instruction in a control memory means; said control memory means connected to said control register for storing the second and remaining micro instructions of respective micro programs; first adddressing means connected to said control memory means, said instruction means and said control register means, responsive to the contents of said instruction register and to the contents of said control register means for successively addressing said control memory means to read out one of the micro instructions of a micro program, corresponding to the macro instruction in the instruction register, into said control register means, said first addressing means supplying the micro instruction having the particular bit pattern to said control register means in synchronism with the reading out of the macro instruction from the main memory; and second addressing means connected between said main memory and said subsidiary control memory means for addressing said subsidiary control memory means to read out the first micro instruction into said control register means in response to the contents of the operation code of the macro instruction read out from the main memory.

Claim 7

A micro program control system as defined in claim 4, wherein said first addressing means comprises: address register means connected to said control memory means for holding the address of a micro instruction to be read out from the control memory means; address selector means connected to said address register means for updating the contents of the address register means; decoder means connected to said instruction register for decoding the operation code of the macro instruction held in said instruction register for supplying first address information to said address selector means; means for incrementing the address value indicated by the address register means for supplying second address information to said address selector means; means for supplying said third address information, represented by the micro instruction in said control register means, to said address selector means; and said address selector means selecting an address signal from among the first, second and third address information provided thereto in response to the contents of said address register means, thereby to supply the address to said address register means.