Patent US4080589A successfully refreshed from Google Patents.
US4080589A
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Error density detector
Assignee: AG Communication Systems Corp
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Filing: 1975-06-02
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Granted: 1978-03-21
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Expires: 1995-06-02
Abstract
Abstract An initial error indicated by a pulse at the binary input is applied through a gating circuit to trigger a monostable multivibrator (one-shot) to start a timing interval. The output of the one-shot is applied to a second gating circuit which inhibits the first gating circuit to prevent retriggering of the one-shot. Subsequent error pulses are then applied directly to a counting mechanism which counts the errors which occur during the predetermined time interval established by the one-shot. An acceptable error density is established by the predetermined time interval for the one-shot in relation to the number of errors that would occur during this predetermined time interval. If the number of errors which occur exceeds the acceptable error density, the counting circuit puts out a signal which may be applied to an alarm (or framing) circuit. Once the error counter produces an output, i.e., exceeds the acceptable error density, the counter applies a binary indication to the second gating circuit which causes the first gating circuit to retrigger the one-shot. Further, each error pulse which occurs before the one-shot times out will now trigger the one-shot. In order for the circuit to reset, an error-free period, equal to the period of the one-shot, must occur.
Inventors
- 👤 Ralph LeRoy Kline
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:19
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; G01R23/15; H; H03; H03K; H03K5/00; H03K5/19
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
123 words
In a digital system, an error density detector which comprises: means responsive to an initial error input signal to set a first predetermined time interval during which errors are to be counted; means for digitally counting each input error signal during said first time interval; said digital counting means providing an output error indication when a predetermined number of errors occur during said first predetermined time interval; means responsive to said error indication to set a second predetermined time interval during which said error indication will remain; and means responsive to each error input signal, which occurs after said error indication and prior to the termination of said second predetermined time interval, to reset said means which sets said second predetermined time interval.
Claim 2
Dependent Claim
123 words
In a digital system, an error density detector which comprises: means responsive to an initial error input signal to set a first predetermined time interval during which errors are to be counted; means for digitally counting each input error signal during said first time interval; said digital counting means providing an output error indication when a predetermined number of errors occur during said first predetermined time interval; means responsive to said error indication to set a second predetermined time interval during which said error indication will remain; and means responsive to each error input signal, which occurs after said error indication and prior to the termination of said second predetermined time interval, to reset said means which sets said second predetermined time interval.
Claim 3
Dependent Claim
18 words
An error density detector of claim 1 wherein said first and second predetermined time intervals are the same.
Claim 4
Dependent Claim
110 words
An error density detector of claim 1 wherein the means responsive to the initial error input signal further comprises: logic means having an input and an output, said input operatively connected to receive said error signals, said logic means responsive to said initial error input signal to provide a logic signal at said output; and timing means having an input operatively connected to the output of said logic means and responsive to the logic signal resulting from said initial error input signal for setting said first predetermined time interval; said timing means having an output operatively connected to said counting means and to a second input to said logic means.
Claim 5
Dependent Claim
16 words
The error density detector of claim 3 wherein said timing means is a retriggerable monostable multivibrator.
Claim 6
Dependent Claim
53 words
The error density detector of claim 3 wherein said digital counting means further comprises: an N-stage shift register having an input connected to a second output of said logic means; said shift register having two outputs, one said output providing said error indication where N errors occur during said first predetermined time interval.
Claim 7
Dependent Claim
75 words
The error density detector of claim 5 wherein said means to set said second predetermined time interval further comprises: means in said logic means responsive to the second output from said counting means, following an error indication, to set and hold said logic means in a state wherein each subsequent error is applied to said timing means to reset the timing means so long as at least one error occurs during said predetermined time interval.
Claim 8
Dependent Claim
110 words
The error density detector of claim 5 wherein said means to set said second predetermined time interval further comprises: means in said logic means responsive to the second output from said counting means, following an error indication, to set and hold said logic means in a state wherein each subsequent error is applied to the timing means so long as at least one error occurs during said second predetermined time interval; and time changing means operatively connected between one output of said counting means and said timing means so that said second predetermined time interval may be set to be less than or greater than said first predetermined time interval.
Claim 9
Dependent Claim
75 words
The error density detector of claim 7 wherein said time changing means further comprises: a resistor means having one end thereof connected to said timing means; and a transistor having a biasing circuit responsive to the output of said counting means so said transistor is not conducting when the output stage of said counting means is in one said state and the transistor is conducting when the output stage is in the other said state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-20 | 1981-09-19 | 1982-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-20 | 1985-09-19 | 1986-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-20 | 1989-09-19 | 1990-03-21 | $7700.00 | Window Closed / Lapsed |