Current mode binary/BCD arithmetic logic unit with parity

Claim 2

A current mode binary/binary coded decimal arithmetic logic unit for performing a repertoire of operations on pure binary and on binary coded decimal data and for performing parity prediction, parity checking, and carry checking operations, said arithmetic logic unit comprising: a first portion for receiving first and second binary signal inputs Ai and Bi, a carry input CIN, a decimal mode signal D, a decimal add signal DA, and a mode control signal M1-M16, said first portion generating a binary output resultant Fi of the operation defined by said mode control signal, said first portion further generating a plurality of intermediate-level signals, a propagate signal P, a generate signal G, and a carry-out signal COUT, a second portion receiving said intermediate-level signals, and further receiving a carry-in duplicate signal CIND, an invert parity signal IP, and a parity check signal PCK, said second portion generating a parity prediction signal FP representing the predicted state of a binary output parity bit FP and further generating an error signal E in the event that an error occurs in the generation of said carry-out signal COUT or said parity prediction signal FP.

Claim 3

The current mode binary/binary coded decimal arithmetic logic unit as recited in claim 1 wherein said first portion generates said intermediate-level signals in accordance with the following tables: Function Intermediate Signals (Zi): for i = 1, 2, 4, 8 Zi = HSi ⊕ (Ci.M16) zi = [HSi ⊕ (Ci.M16)] Corrected B Operand Intermediate Signals (Ei): E1 = b1 e2 = da.(b2) + da.(b2) e4 = da.(b4) + da.(b4.b2 + b4.b2) e8 = da(b8) + da.(b8 + b4 + b2) half Sum, Half Parity, Propagates, and Generates Intermediate Signals (HSi, HPi, Pi, PPi, Gi, GPi: for i = 1, 2, 4, 8 Gi = M8.Ai.Ei + M4.Ai.Ei GPi = M8.Ei.Ai + M1.Ei.Ai Pi = Ai + M2.Ei + M1.Ei PPi = Ei + M2.Ai + M4.Ai HSi = Gi.Pi HPi = GPi.PPi ______________________________________ M8 M4 M2 M1 HSi HPi ______________________________________ 0 0 0 0 Ai Ei 0 0 0 1 Ai + Ei Ai . Ei 0 0 1 0 Ai + Ei Ai + Ei 0 0 1 1 1 Ai ⊕ Ei 0 1 0 0 Ai . Ei Ai + Ei 0 1 0 1 Ei Ai 0 1 1 0 Ai ⊕Ei 1 0 1 1 1 Ai + Ei Ai + Ei 1 0 0 0 Ai . Ei Ai . Ei 1 0 0 1 Ai ⊕ Ei 0 1 0 1 0 Ei Ai 1 0 1 1 Ai + Ei Ai . Ei 1 1 0 0 0 Ai ⊕ Ei 1 1 0 1 Ai . Ei Ai . Ei 1 1 1 0 Ai . Ei Ai + Ei 1 1 1 1 Ai Ei Carry Intermediate Signals (Ci): C1 = CIN C2 = G1 + HS1 . CIN C4 = G2 + HS2 . G1 + HS2 . HS1 . CIN C8 = G4 + HS4 . G2 ++ HS4 . HS2 . G1 ++ HS4 . HS2 . HS1 . CIN ______________________________________ wherein said second portion generates said parity prediction signal FP in accordance with the following table: Parity Output (FP): fp = ZP ⊕ (Z4.Z2.D.COUT) zp = {cin. [hs1 + (hs2.hs4)] .m16} ⊕{g1. (hs2 + hs4).m16} ⊕ {g2.hs4.m16} ⊕ {g4.m16} ⊕ {ip} ⊕ {hs1 ⊕ hs2 ⊕ hs4 ⊕ hs8} and wherein said second portion generates said error signal E in accordance with the following table: Error Output (E): E = {(CIND ⊕ CIN).M16} + {[AP ⊕ BP ⊕ (DA.B4.B2)] ⊕ [hs1 ⊕ hs2 ⊕ hs4 ⊕ hs8] ⊕ [hp1 ⊕ hp2 ⊕ hp4 ⊕ hp8]}.pck