Semiconductor structure with annular collector/subcollector region

Claim 2

A semiconductor structure comprising: a substrate; an annular subcollector region formed by semiconductor material doped with an impurity of a first conductivity type in said substrate; at least one base region formed by semiconductor material doped with an impurity of a second conductivity type over at least a portion of said subcollector region and defining a base-collector PN junction; at least one emitter region formed by semiconductor material doped with an impurity of said first conductivity type substantially in said at least one base region and over said subcollector region and defining a base-emitter PN junction; said annular subcollector region laterally surrounding a region having a higher resistivity than said annular subcollector region, said region of higher resistivity comprising insulating material.

Claim 3

A semiconductor structure as in claim 1 wherein said region having a higher resistivity further comprises: semiconductor material doped with an impurity of said first conductivity type and having an impurity concentration lower than the impurity concentration of said annual subcollector region.

Claim 4

A semiconductor structure as in claim 2 wherein said region of higher resistivity extends to a major surface of said substrate and is adapted for the formation of at least one Schottky barrier diode.

Claim 5

A semiconductor structure as in claim 1 wherein said insulating material comprises: an oxide of silicon.

Claim 6

A semiconductor structure as in claim 4 wherein said oxide of silicon is silicon dioxide formed by in situ conversion of portions of said semiconductor material within the area defined by the outer periphery of said annular subcollector region.

Claim 7

A semiconductor structure as in claim 1 further comprising: an isolating material laterally surrounding said entire structure thereby isolating said structure from other portions of said substrate.

Claim 8

A semiconductor structure as in claim 6 wherein said isolating material comprises an oxide of silicon.

Claim 9

A semiconductor structure as in claim 1 wherein said annular subcollector region defines a polygon, said at least one base region being formed over each section of said polygon, an emitter region being formed in each said at least one base region over each section of said polygon.

Claim 10

A multiemitter integrated semiconductor transistor structure comprising: a semiconductor substrate having first and second major surfaces; an annular subcollector region formed with the semiconductor substrate by highly doping said semiconductor substrate material with an impurity of a first conductivity type; at least one base region formed by semiconductor material doped with an impurity of a second conductivity type over at least a portion of said subcollector region and defining a base-collector P-N junction; an emitter region formed substantially in the at least one base region over at least a portion of the subcollector region by a semiconductor material doped with an impurity of said first conductivity type and defining a base-emitter P-N junction; said annular subcollector region laterally surrounding a region having a higher resistivity than said annular subcollector region; and said region of higher resistivity comprising insulating material.

Claim 11

A multiemitter integrated semiconductor transistor structure comprising: a semiconductor substrate having first and second major surfaces; an annular subcollector region formed with the semiconductor substrate by highly doping said semiconductor substrate material with an impurity of a first conductivity type; at least one base region formed by semiconductor material doped with an impurity of a second conductivity type over at least a portion of said subcollector region and defining a base-collector P-N junction; an emitter region formed substantially in the at least one base region over at least a portion of the subcollector region by a semiconductor material doped with an impurity of said first conductivity type and defining a base-emitter P-N junction; said annular subcollector region laterally surrounding a region having a higher resistivity than said annular subcollector region; and said region of higher resistivity comprising insulating material.

Claim 12

A semiconductor structure as in claim 7 wherein said oxide of silicon is silicon dioxide formed by in situ conversion of portions of said semiconductor material outside an area defined by the inner periphery of said annular subcollector region.

Claim 13

A semiconductor structure as in claim 7 wherein said isolating material comprises, at least in part, a doped isolation region under said oxide of silicon.

Claim 14

A multiemitter integrated semiconductor transistor structure as in claim 9 having an epitaxial layer over at least a portion of said substrate, said at least one base region, said base-collector P-N junction, said emitter region, and said base-emitter P-N junction being formed in said epitaxial layer.

Claim 15

A multiemitter integrated semiconductor transistor structure as in claim 9 wherein said region having a higher resistivity comprises: semiconductor material doped with an impurity of said first conductivity type and having an impurity concentration lower than the impurity concentration of said annular subcollector region.

Claim 16

A multiemitter integrated semiconductor transistor structure as in claim 13 wherein said region of higher resistivity extends to a major surface of said substrate and is adapted for the formation of at least one Schottky barrier diode.

Claim 17

A multiemitter integrated semiconductor transistor structure as in claim 9 wherein said insulating material comprises: an oxide of silicon.

Claim 18

A multiemitter integrated semiconductor transistor structure as in claim 15 wherein said oxide of silicon is silicon dioxide formed by in situ conversion of portions of said semiconductor material within an area defined by the outer periphery of said annular subcollector region.

Claim 19

A multiemitter integrated semiconductor transistor structure as in claim 9 further comprising: an isolating material laterally surrounding said entire structure thereby isolating said structure from other portions of said substrate.

Claim 20

A multiemitter integrated semiconductor transistor structure as in claim 17 wherein said isolating material comprises, an oxide of silicon.

Claim 21

A multiemitter integrated semiconductor transistor structure as in claim 18 wherein said oxide of silicon is silicon dioxide formed by in situ conversion of portions of said semiconductor material outside an area defined by the inner periphery of said subcollector region.

Claim 22

A multiemitter integrated semiconductor transistor structure as in claim 18 wherein said isolating material comprises, at least in part, a doped isolation region under said oxide of silicon.

Claim 23

A multiemitter integrated semiconductor transistor structure as in claim 9 wherein said annular subcollector region defines a polygon, said at least one base region formed over each section of said polygon, an emitter region being formed in each said at least one base region over each section of said polygon.