US4079332A
Expired / Lapsed
US
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High gain differential amplifier
Assignee: Boeing North American Inc
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Filing: 1976-11-22
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Granted: 1978-03-14
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Expires: 1996-11-22
Abstract
Abstract A high gain, field effect transistor differential amplifier including first and second cascade connected inverter stages and a feedback controlled source of current connected to each of the stages. High voltage gain is achieved by virtue of a positive feedback path connected between an output terminal of the differential amplifier and the source of current so that the current in each inverter stage is controlled.
Inventors
- 👤 Clarence W. Padgett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:27
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F2203/00; H03F2203/45; H03F2203/45626; H03F2203/45658
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
227 words
In combination: first, second, third and fourth multi-terminal semiconductor devices having respective conduction path terminals and a control terminal, the conduction paths of the first and second of said multi-terminal devices connected in a first series circuit, the conduction paths of the third and fourth of said multiterminal devices connected in a second series circuit, said first and second series circuits connected together to form a first electrical junction with a source of relatively positive reference potential, a first output terminal connected to both the control terminal of said first device and to the first series circuit formed by the conduction paths of said first and second devices, a second output terminal connected to both the control terminal of said third device and to the second series circuit formed by the conduction paths of said third and fourth devices, first and second input terminals respectively connected to the control terminals of said second and fourth devices, a fifth multi-terminal semiconductor device having conduction path terminals and a control terminal, said fifth multi-terminal semiconductor device connected between a source of relatively negative reference potential and a second electrical junction formed by the connection together of said first and second series circuits, and positive feedback means connected between said first output terminal and the control terminal of said fifth multi-terminal device to control the conductivity of said fifth device.
Claim 2
Dependent Claim
227 words
In combination: first, second, third and fourth multi-terminal semiconductor devices having respective conduction path terminals and a control terminal, the conduction paths of the first and second of said multi-terminal devices connected in a first series circuit, the conduction paths of the third and fourth of said multiterminal devices connected in a second series circuit, said first and second series circuits connected together to form a first electrical junction with a source of relatively positive reference potential, a first output terminal connected to both the control terminal of said first device and to the first series circuit formed by the conduction paths of said first and second devices, a second output terminal connected to both the control terminal of said third device and to the second series circuit formed by the conduction paths of said third and fourth devices, first and second input terminals respectively connected to the control terminals of said second and fourth devices, a fifth multi-terminal semiconductor device having conduction path terminals and a control terminal, said fifth multi-terminal semiconductor device connected between a source of relatively negative reference potential and a second electrical junction formed by the connection together of said first and second series circuits, and positive feedback means connected between said first output terminal and the control terminal of said fifth multi-terminal device to control the conductivity of said fifth device.
Claim 3
Dependent Claim
23 words
The combination recited in claim 1, wherein each of said first, second, third and fourth multi-terminal semiconductor devices is a field effect transistor.
Claim 4
Dependent Claim
31 words
The combination recited in claim 2, wherein said first and third field effect transistors are depletion mode transistor devices and said second and fourth field effect transistors are enhancement mode devices.
Claim 5
Dependent Claim
17 words
The combination recited in claim 1, wherein said fifth multi-terminal semiconductor device is a field effect transistor.
Claim 6
Dependent Claim
16 words
The combination recited in claim 4, wherein said field effect transistor is an enhancement mode device.
Claim 7
Dependent Claim
16 words
The combination recited in claim 4, wherein said field effect transistor operates as a current source.
Claim 8
Dependent Claim
38 words
The combination recited in claim 1, wherein said first and second multi-terminal devices form a first inverter stage and said third and fourth multi-terminal devices form a second inverter stage, said first and second inverter stages cascaded together.
Claim 9
Dependent Claim
156 words
A high gain differential amplifier comprising: a first inverter stage including first series connected depletion and enhancement mode transistor devices, a second inverter stage including second series connected depletion and enhancement mode transistor devices, said first and second inverter stages cascaded together between first and second electrical junctions, voltage source means connected to each of said inverter stages at a first of said electircal junctions, each of said inverter stages having respective input and output terminal means, current source means comprising an additional enhancement mode transistor device connected to each of said inverter stages at the second of said electrical junctions, and positive feedback means connecting the control terminal of said additional enhancement mode transistor device with the control terminal of said first inverter stage depletion mode transistor device and a point between the first series connected depletion and enhancement mode transistor devices of said first inverter stage to maximize the gain of said differential amplifier.
Claim 10
Dependent Claim
156 words
A high gain differential amplifier comprising: a first inverter stage including first series connected depletion and enhancement mode transistor devices, a second inverter stage including second series connected depletion and enhancement mode transistor devices, said first and second inverter stages cascaded together between first and second electrical junctions, voltage source means connected to each of said inverter stages at a first of said electircal junctions, each of said inverter stages having respective input and output terminal means, current source means comprising an additional enhancement mode transistor device connected to each of said inverter stages at the second of said electrical junctions, and positive feedback means connecting the control terminal of said additional enhancement mode transistor device with the control terminal of said first inverter stage depletion mode transistor device and a point between the first series connected depletion and enhancement mode transistor devices of said first inverter stage to maximize the gain of said differential amplifier.
References Cited (Backward Citations)
US3882409A
Cited
US3970951A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-13 | 1981-09-12 | 1982-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-13 | 1985-09-12 | 1986-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-13 | 1989-09-12 | 1990-03-14 | $7700.00 | Window Closed / Lapsed |