Differential amplifier circuit

Claim 2

A differential amplifier circuit comprising: a power supply source having first and second voltage terminals; signal input means for providing differential input signal voltages; and at least a first differential amplifier unit including first, second and third field effect transistors each having gate, source and drain electrodes, means connecting the drain-source paths of said first and second field effect transistors in parallel with each other and in series with the drain-source path of said third field effect transistor between said first and second voltage terminals, means for applying said differential input signal voltages to the gate electrodes of said first and second field effect transistors, a signal output terminal connected to said drain electrode of said second field effect transistor for providing an amplified output signal, and a feedback loop connected between said drain electrode of said first field effect transistor and said gate electrode of said third field effect transistor for providing negative feedback in respect to common changes in the currents through the drain electrodes of said first and second field effect transistors and positive feedback in respect to the amplification of said differential input signal voltages.

Claim 3

A differential amplifier circuit according to claim 1; wherein said signal input means includes a Hall-effect device having a pair of input terminals connected between said first and second voltaGe terminals and a pair of output terminals respectively connected to the gate electrodes of said first and second field effect transistors.

Claim 4

A differential amplifier circuit according to claim 2; wherein at least said first, second and third field effect transistors and said Hall-effect device form an integrated circuit on a single semiconductor wafer.

Claim 5

A differential amplifier circuit according to claim 1; further comprising second and third differential amplifier units each of which is similar to said first differential amplifier unit; and in which said signal input means includes first and second signal sources respectively providing differential input signal voltages of opposed polarities, the differential input signal voltages from said first signal source are applied to the gate electrodes of said first and second field effect transistors in said first differential amplifier unit and the differential input signal voltages from said second signal source are applied to the gate electrodes of said first and second field effect transistors in said second differential amplifier unit so that the amplified output signals from said first and second differential amplifier units are of opposite polarity, and the signal output terminals of said first and second differential amplifier units are respectively connected to the gate electrodes of said first and second field effect transistors of said third differential amplifier unit so that said amplified output signals from said first and second differential amplifier units provide the differential input signal voltages for said third differential amplifier unit.

Claim 6

A differential amplifier circuit according to claim 4; in which each of said first and second signal sources includes a Hall-effect device having a pair of input terminals connected between said first and second voltage terminals and a pair of output terminals respectively connected to the gate electrodes of said first and second field effect transducers of the corresponding one of said first and second differential amplifier units.

Claim 7

A differential amplifier circuit according to claim 5; in which at least said first, second and third field effect transistors of said first, second and third differential amplifier units and the Hall-effect devices of said first and second input signal sources form an integrated circuit on a single semiconductor wafer.

Claim 8

A differential amplifier circuit comprising: a power supply source having first and second voltage terminals; first, second and third field effect transistors each having gate, source and drain electrodes; signal input means providing differential input signal voltages applied to the gate electrodes of said first and second field effect transistors; first and second resistors connected between the drain electrodes of said first and second field effect transistors, respectively, and said first voltage terminal; circuit means for commonly connecting the source electrodes of said first and second field effect transistors to the drain electrode of said third field effect transistor; circuit means for connecting the source electrode of said third field effect transistor to said second voltage terminal; a feedback loop connecting the drain electrode of said first field effect transistor to the gate electrode of said third field effect transistor; and signal output means connected to the drain electrode of said second field effect transistor; whereby said feedback loop provides negative feedback for a common change of currents through the drain electrodes of said first and second field effect transistors and provides positive feedback for the amplification of the differential input signal voltages from said signal input means.

Claim 9

A differential amplifier circuit comprising: a power supply source having first and second voltage terminals; first, second and third field effect transistors each having gate, source and drain electrodes; signal input means providing differential input signal voltages applied to the gate electrodes of said first and second field effect transistors; first and second resistors connected between the drain electrodes of said first and second field effect transistors, respectively, and said first voltage terminal; circuit means for commonly connecting the source electrodes of said first and second field effect transistors to the drain electrode of said third field effect transistor; circuit means for connecting the source electrode of said third field effect transistor to said second voltage terminal; a feedback loop connecting the drain electrode of said first field effect transistor to the gate electrode of said third field effect transistor; and signal output means connected to the drain electrode of said second field effect transistor; whereby said feedback loop provides negative feedback for a common change of currents through the drain electrodes of said first and second field effect transistors and provides positive feedback for the amplification of the differential input signal voltages from said signal input means.

Claim 10

A differential amplifier circuit according to claim 7; wherein said signal input means includes a Hall-effect device having a pair of input terminals connected between said first and second voltage terminals and a pair of output terMinals respectively connected to the gate electrodes of said first and second field effect transistors.

Claim 11

A differential amplifier circuit according to claim 8; wherein at least said first, second and third field effect transistors and said Hall-effect device form an integrated circuit on a single semiconductor wafer.

Claim 12

A differential amplifier circuit comprising: a power supply source having first and second voltage terminals; first, second and third differential amplifier units each of which comprises first, second and third field effect transistors each having gate, source and drain electrodes, circuit means connected between the drain electrode of said first field effect transistor and said first voltage terminal, a resistor connected between the drain electrode of said second field effect transistor and said first voltage terminal, circuit means for connecting the source electrodes of said first and second field effect transistors to the drain electrode of said third field effect transistor, circuit means for connecting the source electrode of said third field effect transistor to said second voltage terminal, means for biasing the gate electrode of said third field effect transistor, and signal output means connected to the drain electrode of said second field effect transistor; first signal input means providing differential input signal voltages to the gate electrodes of said first and second field effect transistors of said first differential amplifier unit; second signal input means providing differential input signal voltages which are differential in respect to the input signal voltages from said first signal input means and which are applied to the gate electrodes of said first and second field effect transistors, respectively, of said second differential amplifier unit so that the output signals from the signal output means of said first and second differential amplifier circuits are differential to each other; and circuit means connecting the signal output means of said first and second differential amplifier circuits to the gate electrodes of the first and second field effect transistors, respectively, of said third differential amplifier circuit.

Claim 13

A differential amplifier circuit comprising: a power supply source having first and second voltage terminals; first, second and third differential amplifier units each of which comprises first, second and third field effect transistors each having gate, source and drain electrodes, circuit means connected between the drain electrode of said first field effect transistor and said first voltage terminal, a resistor connected between the drain electrode of said second field effect transistor and said first voltage terminal, circuit means for connecting the source electrodes of said first and second field effect transistors to the drain electrode of said third field effect transistor, circuit means for connecting the source electrode of said third field effect transistor to said second voltage terminal, means for biasing the gate electrode of said third field effect transistor, and signal output means connected to the drain electrode of said second field effect transistor; first signal input means providing differential input signal voltages to the gate electrodes of said first and second field effect transistors of said first differential amplifier unit; second signal input means providing differential input signal voltages which are differential in respect to the input signal voltages from said first signal input means and which are applied to the gate electrodes of said first and second field effect transistors, respectively, of said second differential amplifier unit so that the output signals from the signal output means of said first and second differential amplifier circuits are differential to each other; and circuit means connecting the signal output means of said first and second differential amplifier circuits to the gate electrodes of the first and second field effect transistors, respectively, of said third differential amplifier circuit.

Claim 14

A differential amplifier circuit according to claim 10; in which said circuit means connected between the drain electrode of said first field effect transistor and said first voltage terminal includes a resistor, and the drain electrode of said first field effect transistor is connected to the gate electrode of said third field effect transistor in each of said differential amplifier units.

Claim 15

A differential amplifier circuit according to claim 11; in which said first signal input means includes a first Hall-effect device having a pair of terminals connected between said first and second voltage terminals and a pair of output terminals connected between the gate electrodes of said first and second field effect transistors of said first differential amplifier unit, and said second signal input means includes a second Halleffect device having a pair of terminals connected between said first and second voltage terminals and a pair of output terminals connected between the gate electrodes of said first and second field effect transistors of said second differential amplifier unit.

Claim 16

A differential amplifier circuit according to claim 12; in which at least said first, second and third differential amplifier units and said first and second Hall-effect devices form an integrated circuit on a single semiconductor wafer.

Claim 17

A differential amplifier circuit according to claim 11; in which said first and second signal input means respectively include first and second Hall-effect devices each having a pair of terminals connected between said first and second voltage terminals and a pair of output terminals, one of the output terminals of each of said first and second Hall-effect devices being connected to the gate electrodes of Said first and second field effect transistors of said first differential amplifier circuit, respectively, and the other output terminals of each of said first and second Hall-effect devices being connected to the gate electrodes of said first and second field effect transistors of said second differential amplifier circuit.

Claim 18

A differential amplifier circuit according to claim 14; in which at least said first, second and third differential amplifier circuits and said first and second Hall-effect devices form an integrated circuit on a single semiconductor wafer.

Claim 19

A differential amplifier circuit according to claim 11; in which said first and second signal input means are constituted by a single Hall-effect device having a pair of input terminals connected between said first and second voltage terminals and first and second pairs of output terminals for respectively providing said differential input signal voltages from said first and second signal input means.