Patent US3087422A successfully refreshed from Google Patents.
Patent US4075577A successfully refreshed from Google Patents.
US4075577A
Expired / Lapsed
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Analog-to-digital conversion apparatus
Assignee: International Business Machines Corp
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Filing: 1974-12-30
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Granted: 1978-02-21
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Expires: 1994-12-30
Abstract
Abstract An improvement over an analog-to-digital converter in which a phase-locked loop (including a voltage controlled oscillator, a feedback path, and a phase discriminator) supplies clocking signals to a counter. The clocking signals are gated to the counter by a circuit which energizes a gate in response to a known reference signal and deenergizes an gate in response to the unknown source signal. The resultant count in a measure of the phase difference between the source and reference signals. Accuracy and stability derive from maintenance of a predetermined phase-locked relationship between a signal derived through frequency division of the loop output signal and the cyclic reference signal which is the reference for gating the counts to the counter. The loop output frequency is a harmonic of the frequency of the reference signal. Feedback phase control is developed through interaction of the frequency divided loop output signal with the reference signal in the phase discriminator circuit. The present invention improves the accuracy of the phase-locked loop by making the voltage controlled oscillator ripple waveform linear. This is accomplished by placing a frequency divider in series with the loop, another identical frequency divider in the feedback path, and using an integrator to filter the phase discriminator output.
Inventors
- 👤 Ernest Lee Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:08
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
152 words
In a frequency multiplication circuit having a continuously running VCO (voltage controlled oscillator), arranged in a phase locked loop controlled by a phase discriminator, for producing clock oscillation signals at a pedetermined harmonic of the frequency of recurrence of a cyclic reference signal -- said clock oscillations being used intermittently for developing an encoded digital count representative of an analog magnitude, over discrete interval segments of a cycle of said reference input -- the improvement comprising: means in said phase discriminator for constraining variations in the VCO control input, during said discrete interval segments of said cycle, to a predetermined form giving rise to invariably nullifying error contributions to said magnitude representation; said constraining means offsetting lock and capture properties of said loop from a desired norm; and means associated with inputs to said phase discriminator for compensating for said lock and capture offset caused by the introduction of said constraining means.
Claim 2
Dependent Claim
152 words
In a frequency multiplication circuit having a continuously running VCO (voltage controlled oscillator), arranged in a phase locked loop controlled by a phase discriminator, for producing clock oscillation signals at a pedetermined harmonic of the frequency of recurrence of a cyclic reference signal -- said clock oscillations being used intermittently for developing an encoded digital count representative of an analog magnitude, over discrete interval segments of a cycle of said reference input -- the improvement comprising: means in said phase discriminator for constraining variations in the VCO control input, during said discrete interval segments of said cycle, to a predetermined form giving rise to invariably nullifying error contributions to said magnitude representation; said constraining means offsetting lock and capture properties of said loop from a desired norm; and means associated with inputs to said phase discriminator for compensating for said lock and capture offset caused by the introduction of said constraining means.
Claim 3
Dependent Claim
23 words
The improvement of claim 1 wherein said predetermined form is linear and said constraining means includes successive Exclusive-OR and pulse integration circuit stages.
Claim 4
Dependent Claim
29 words
The improvement of claim 2 wherein said compensating means comprises conprises identical frequency division circuit stages interposed in reference and feedback paths associated with inputs to said Exclusive-OR stage.
Claim 5
Dependent Claim
204 words
In circuit apparatus for converting a variable analog voltage to a digital count representation, said apparatus including an encode counter receiving intermittently gated clock oscillations under control of transitional phases of cyclically recurrent ramp timing signals having alternately positive and negative slope phases, said representation developing over an encoding/counting cycle coincident with one cycle of said ramp signals -- said clock oscillations produced by a VCO in a phase locked loop frequency multiplication circuit, said VCO tracking a harmonic of the recurrence frequency of said ramp timing signals, said loop including a phase discrimination circuit stage providing a varying control voltage, to control the frequency of said VCO, in response to phase differences between reference input signals synchronous with said ramp signals and loop feedback signals derived by frequency division of the VCO clock output -- the improvement, for nullifying encoding errors due to deviation from a predetermined form of the form of variation of the VCO control input over a said encoding/counting cycle, comprising: circuits in said phase discrimination stage for constraining variations in the VCO control input to said predetermined form over each encoding cycle; whereby error contributions to the final encoded count, due to said variations, are nullifying over said cycle.
Claim 6
Dependent Claim
204 words
In circuit apparatus for converting a variable analog voltage to a digital count representation, said apparatus including an encode counter receiving intermittently gated clock oscillations under control of transitional phases of cyclically recurrent ramp timing signals having alternately positive and negative slope phases, said representation developing over an encoding/counting cycle coincident with one cycle of said ramp signals -- said clock oscillations produced by a VCO in a phase locked loop frequency multiplication circuit, said VCO tracking a harmonic of the recurrence frequency of said ramp timing signals, said loop including a phase discrimination circuit stage providing a varying control voltage, to control the frequency of said VCO, in response to phase differences between reference input signals synchronous with said ramp signals and loop feedback signals derived by frequency division of the VCO clock output -- the improvement, for nullifying encoding errors due to deviation from a predetermined form of the form of variation of the VCO control input over a said encoding/counting cycle, comprising: circuits in said phase discrimination stage for constraining variations in the VCO control input to said predetermined form over each encoding cycle; whereby error contributions to the final encoded count, due to said variations, are nullifying over said cycle.
Claim 7
Dependent Claim
81 words
Apparatus according to claim 4 wherein said reference input signals are binary pulses and said form constraining circuits in said phase discrimination stage comprise successive Exclusive-OR and pulse integration circuit stages; said apparatus including identical first and second frequency division circuit stages interposed seriately in the paths of the reference input and feedback input to said phase discrimination stage to compensate for offset of lock and capture characteristics of said phase locked loop due to the introduction of said Exclusive-OR stage.
References Cited (Backward Citations)
US3130376A
Cited
US3247491A
Cited
GB1113843A
Cited
US3435367A
Cited
US3731219A
Cited
US3805182A
Cited
US3879676A
Cited
US3805192A
Cited
US3914760A
Cited
US3883817A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-20 | 1981-08-22 | 1982-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-20 | 1985-08-22 | 1986-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-20 | 1989-08-22 | 1990-02-21 | $7700.00 | Window Closed / Lapsed |