Accurate and stable encoding with low cost circuit elements

Claim 2

An analog voltage to time-based digital count converter comprising: sources of +, - and null reference voltages; a source of unknown voltage to be encoded; a first closed loop circuit for generating a cyclically recurrent bipolar ramp voltage signal having alternate positive and negative slope in each cycle of recurrence; said first closed loop circuit including a high-low comparison section responsive to said ramp and + and - reference voltages for producing a cyclic binary pulse reference signal and an integrating section in tandem with said comparison section for integrating said binary pulse signal to develop said ramp signal; a second closed loop circuit for continuously generating clock oscillations, at a fixed harmonic of the recurrence frequency of said ramp signal; said second loop including: a voltage controlled clock oscillator, a feedback divider coupled to the output of said oscillator for generating feedback signals, at a fixed subharmonic of the frequence of oscillation of said oscillator and a phase detector responsive to phase differences between said binary pulse reference signals and said feedback signals for producing frequency control signals for constraining said oscillations to said fixed harmonic of the ramp frequency; and means for utilizing said ramp signal relative to said +, -, null and unknown voltages for developing timed gating pulses defining segmental intervals, within successive rise and fall slope phases of a cycle of said ramp signal, having a cumulative time duration within said ramp cycle corresponding to the magnitude of said unknown voltage; said gating pulses being thereby useful for controlling digital counting of said clock oscillations to produce a recurrent digital representation of said unknown voltAge, which can be made essentially insensitive to fluctuations in clock oscillator conditions and ramp slope and timing.

Claim 3

In an analog voltage encoder subject to all-solid-state packaging and having means for encoding an unknown analog quantity by deriving a time measurement and corresponding digital count representing said quantity, the improvement comprising: a source of linear bipolar ramp voltage signals alternating cyclically between predetermined positive and negative voltage levels, with predetermined positive and negative slope characteristics in successive time interval segments T1 and T2 of each alternation cycle; wherein the period of the alternation cycle is the sum of T1 and T2, and T1 and T2 are predetermined non-zero and not necessarily equal intervals; circuit means responsive to said unknown analog quantity and said ramp, during each said interval T1 and T2, for producing binary time selection control signals related to transitional phases of said ramp signals, relative to known references and said quantity, and a frequency control signal used to generate said ramp signals; a phase locked frequency multiplication circuit controlled by said frequency control signal for continuously generating clock pulse oscillations which are locked in predetermined harmonic frequency relationship with the cyclic frequency of said ramp signal; and selection circuit means responsive to said selection control signals to control repetitive generation of said count representation in each ramp cycle by controlling cumulative counting of said clock pulses for two discrete periods of each said ramp cycle - said discrete periods corresponding to varied time sub-segments of said interval segments T1 and T2 of the cycle during which the ramp is between transitional signal levels representing the unknown analog quantity and a zero reference - and by controlling readout and resetting of said count after the end of the sub-segment in T2 and before the sub-segment in T1 of the following cycle; whereby a count, accurately representative of said analog quantity and insensitive to differences between T1 and T2 in a cycle and to irregularities of circuit components of said ramp and clock oscillation generating circuits, is developed cumulatively over each ramp cycle.

Claim 4

In an analog voltage encoder subject to all-solid-state packaging and having means for encoding an unknown analog quantity by deriving a time measurement and corresponding digital count representing said quantity, the improvement comprising: a source of linear bipolar ramp voltage signals alternating cyclically between predetermined positive and negative voltage levels, with predetermined positive and negative slope characteristics in successive time interval segments T1 and T2 of each alternation cycle; wherein the period of the alternation cycle is the sum of T1 and T2, and T1 and T2 are predetermined non-zero and not necessarily equal intervals; circuit means responsive to said unknown analog quantity and said ramp, during each said interval T1 and T2, for producing binary time selection control signals related to transitional phases of said ramp signals, relative to known references and said quantity, and a frequency control signal used to generate said ramp signals; a phase locked frequency multiplication circuit controlled by said frequency control signal for continuously generating clock pulse oscillations which are locked in predetermined harmonic frequency relationship with the cyclic frequency of said ramp signal; and selection circuit means responsive to said selection control signals to control repetitive generation of said count representation in each ramp cycle by controlling cumulative counting of said clock pulses for two discrete periods of each said ramp cycle - said discrete periods corresponding to varied time sub-segments of said interval segments T1 and T2 of the cycle during which the ramp is between transitional signal levels representing the unknown analog quantity and a zero reference - and by controlling readout and resetting of said count after the end of the sub-segment in T2 and before the sub-segment in T1 of the following cycle; whereby a count, accurately representative of said analog quantity and insensitive to differences between T1 and T2 in a cycle and to irregularities of circuit components of said ramp and clock oscillation generating circuits, is developed cumulatively over each ramp cycle.

Claim 5

An analog to digital converter, in which an analog signal parameter of variable magnitude is represented by a digital count developed over a time interval having a duration related linearly to the variable magnitude, comprising: a source of cyclically recurrent reference signals having a predetermined cyclically recurrent transitional phase state; a source of said variable analog parameter presented in a signal form which is cyclically time measurable relative to said reference signals; a frequency multiplication circuit having a continuously running voltage controlled oscillator in a phase locked loop for producing clock oscillation signals at a predetermined harmonic of the frequency of reference signal recurrence; said circuit including: a frequency divider receiving said clock oscillations and generating a divided output frequency corresponding to the frequency of recurrence of said reference signals, and a phase discriminator responsive to phase differences between the output of said divider and the reference signals for producing control voltages for constraining said clock oscillations to said predetermined harmonic frequency, regardless of jitter or drift tendencies in said oscillator; means for utilizing said reference and variable signals to develop variably timed gating signals useful to control repetitive gating of said clock oscillations for development of said digital count representation; said gating signals having short duration by comparison to the length of a reference signal cycle; said reference and analog signals being causatively unrelated to any motion effect; said reference signal generating Circuit comprising a first circuit for producing cyclically recurrent bipolar ramp signal oscillations having predetermined alternately positive and negative slope in each recurrence cycle, and a second circuit for supplying cyclically recurrent binary pulse reference signals to the first circuit; said first and second circuits being connected in a closed loop; said ramp signals and analog signals being used to develop said gating signals for controlling the development of said digital count and said reference signals being used for controlling said clock oscillation frequency.

Claim 6

An analog to digital converter, in which an analog signal parameter of variable magnitude is represented by a digital count developed over a time interval having a duration related linearly to the variable magnitude, comprising: a source of cyclically recurrent reference signals having a predetermined cyclically recurrent transitional phase state; a source of said variable analog parameter presented in a signal form which is cyclically time measurable relative to said reference signals; a frequency multiplication circuit having a continuously running voltage controlled oscillator in a phase locked loop for producing clock oscillation signals at a predetermined harmonic of the frequency of reference signal recurrence; said circuit including: a frequency divider receiving said clock oscillations and generating a divided output frequency corresponding to the frequency of recurrence of said reference signals, and a phase discriminator responsive to phase differences between the output of said divider and the reference signals for producing control voltages for constraining said clock oscillations to said predetermined harmonic frequency, regardless of jitter or drift tendencies in said oscillator; means for utilizing said reference and variable signals to develop variably timed gating signals useful to control repetitive gating of said clock oscillations for development of said digital count representation; said gating signals having short duration by comparison to the length of a reference signal cycle; said reference and analog signals being causatively unrelated to any motion effect; said reference signal generating Circuit comprising a first circuit for producing cyclically recurrent bipolar ramp signal oscillations having predetermined alternately positive and negative slope in each recurrence cycle, and a second circuit for supplying cyclically recurrent binary pulse reference signals to the first circuit; said first and second circuits being connected in a closed loop; said ramp signals and analog signals being used to develop said gating signals for controlling the development of said digital count and said reference signals being used for controlling said clock oscillation frequency.