Abstract A device for providing phase synchronism of a transit station in a digital telecommunication network, comprising within a phase-locked loop a voltage-controlled oscillator that has an output arranged to supply a station clock signal and a control input actuated by line clock signals pertaining to a plurality of incoming lines from other transit stations in the telecommunication network and a phase comparator that is arranged to compare the phase of the station clock signal with the phases of the line clock signals and has an output connected to the control input of the voltage-controlled oscillator via a loop filter. The loop filter comprises a memory means that has an address input and a read output and is arranged to store selected weighting coefficients for the line clock signals, and address counter means that has an input connected to the output of the voltage-controlled oscillator and an output arranged for cyclically reading out address words assigned to said incoming lines and being connected to the address input of the memory means, and a multiplier means that has a first input connected to the output of the phase comparator, a second input connected to the read output of the memory means and an output connected to the control input of the voltage-controlled oscillator via an averaging means, a time multiplex stage being connected between said incoming lines and the phase comparator and having an address input connected to the output of the address counter means.
Device for providing phase synchronism of a transit station in a digital telecommunication network, comprising within a phase-locked loop a voltage-controlled oscillator that has an output arranged to supply a station clock signal and a control input capable of being actuated upon by line clock signals pertaining to a plurality of incoming lines from other transit stations in the telecommunication network and a phase comparator that is arranged to compare the phase of the station clock signal with the phases of the line clock signals and has an output connected to the control input of the voltage controlled oscillator via a loop filter, wherein the loop filter comprises a memory means which has an address input and a read output and is arranged to store selected weighting coefficients for the line clock signals, an address counter means which has an input connected to the output of the voltage-controlled oscillator and an output arranged for a cyclical read out of address words allotted to said incoming lines and connected to the address input of the memory means, and a multiplier means which has a first input connected to the output of the phase comparator, a second input connected to the read output of the memory means and an output connected to the control input of the voltage-controlled oscillator via an averaging means, a time multiplexor stage being connected between said incoming lines and the phase comparator and having an address input connected to the output of the address counter means.
Claim 2
Dependent Claim
249 words
Device for providing phase synchronism of a transit station in a digital telecommunication network, comprising within a phase-locked loop a voltage-controlled oscillator that has an output arranged to supply a station clock signal and a control input capable of being actuated upon by line clock signals pertaining to a plurality of incoming lines from other transit stations in the telecommunication network and a phase comparator that is arranged to compare the phase of the station clock signal with the phases of the line clock signals and has an output connected to the control input of the voltage controlled oscillator via a loop filter, wherein the loop filter comprises a memory means which has an address input and a read output and is arranged to store selected weighting coefficients for the line clock signals, an address counter means which has an input connected to the output of the voltage-controlled oscillator and an output arranged for a cyclical read out of address words allotted to said incoming lines and connected to the address input of the memory means, and a multiplier means which has a first input connected to the output of the phase comparator, a second input connected to the read output of the memory means and an output connected to the control input of the voltage-controlled oscillator via an averaging means, a time multiplexor stage being connected between said incoming lines and the phase comparator and having an address input connected to the output of the address counter means.