Semiconductor read-only memory

Claim 2

A read-only memory comprising: a first and a second line; a plurality of information memory circuits connected in parallel with one another across said first and second lines, each said memory circuit comprising a pair of insulated-gate field effect transistors connected in series with each other across said first and second lines, one of said insulated-gate field effect transistors in each said information memory circuit in which information is to be written being of depletion mode, while the other said insulated-gate field effect transistor being of enhancement mode; means for supplying electric power to said information memory circuits; and means for reading out the information written in said information memory circuits.

Claim 3

A read-only memory as claimed in claim 1, wherein said reading means comprises a load means connected at one terminal thereof to said first line and is connected in series with all said information memory circuits, and said electric power is supplied to said information memory circuits through said load means, whereby the information written in said information memory circuits is read out to appear on said first line.

Claim 4

A read-only memory as claimed in claim 2, wherein said load means comprises an insulated-gate field effect transistor of depletion mode having its gate connected to its source.

Claim 5

A read-only memory as claimed in claim 2, wherein said insulated-gate field effect transistors of enhancement mode in said information memory circuits are respectively connected at the gate thereof to associated address lines, whereby said information memory circuits from which the information is to be read out are selected by control signals applied to said address lines.

Claim 6

A read-only memory as claimed in claim 1, wherein said reading means comprises a switching means connected at one terminal thereof to the connection point of said two series-connected insulated-gate field effect transistors constituting each said information memory circuit, whereby the information written in said information memory circuits is read out through said switching means to appear at the other terminal of said switching means.

Claim 7

A read-only memory as claimed in claim 5, wherein said switching means comprises an insulated-gate field effect transistor of enhancement mode.

Claim 8

A read-only memory comprising: a line for deriving an output signal of the memory; a second and a third line for supplying electric power; a plurality of address lines for applying address signals; a plurality of information memory circuits associated with the corresponding ones of said address lines and connected in parallel with one another across said first and second lines, each said information memory circuit including a series connection of a first insulated-gate field effect transistor of enhancement mode connected at the gate thereof to one of said address lines and a second insulated-gate field effect transistor having the gate and source thereof connected to each other and having the operating mode thereof selected to be of either one of enhancement mode and depletion mode depending on the information to be stored; and a third insulated-gate field effect transistor connected across said first and third lines to function as a load for said information memory circuits; whereby the information stored in said information memory circuits is read out to appear as an output signal on said first line in response to the application of the address signals to said address lines.

Claim 9

A read-only memory comprising: a line for deriving an output signal of the memory; a second and a third line for supplying electric power; a plurality of address lines for applying address signals; a plurality of information memory circuits associated with the corresponding ones of said address lines and connected in parallel with one another across said first and second lines, each said information memory circuit including a series connection of a first insulated-gate field effect transistor of enhancement mode connected at the gate thereof to one of said address lines and a second insulated-gate field effect transistor having the gate and source thereof connected to each other and having the operating mode thereof selected to be of either one of enhancement mode and depletion mode depending on the information to be stored; and a third insulated-gate field effect transistor connected across said first and third lines to function as a load for said information memory circuits; whereby the information stored in said information memory circuits is read out to appear as an output signal on said first line in response to the application of the address signals to said address lines.

Claim 10

A read-only memory comprising: a first line; a second line; a plurality of information memory circuits connected in parallel with one another across said first and second lines, each memory circuit storing prescribed information therein to be non-destructively read-out when selectively addressed, each memory circuit comprising a series connection of a first field effect of the enhancement type and means for defining the information stored in the memory circuit, said defining means being formed of a second field effect transistor of one of the enhancement and depletion type, which one type effectively defines the information stored in the memory circuit; means for supplying electric power to said information memory circuits; and means, coupled to each of said memory circuits, for selectively addressing each respective circuit and thereby causing the information stored therein to be non-destructively read-out.

Claim 11

A read-only memory comprising: a first line; a second line; a plurality of information memory circuits connected in parallel with one another across said first and second lines, each memory circuit storing prescribed information therein to be non-destructively read-out when selectively addressed, each memory circuit comprising a series connection of a first field effect of the enhancement type and means for defining the information stored in the memory circuit, said defining means being formed of a second field effect transistor of one of the enhancement and depletion type, which one type effectively defines the information stored in the memory circuit; means for supplying electric power to said information memory circuits; and means, coupled to each of said memory circuits, for selectively addressing each respective circuit and thereby causing the information stored therein to be non-destructively read-out.