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US4073006A
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Digital processor system with simultaneous branch and OP code function
Assignee: Texas Instruments Inc
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Filing: 1976-07-19
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Granted: 1978-02-07
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Expires: 1996-07-19
Abstract
Abstract An electronic digital processor is disclosed of the type used in miniature calculators. The processor is fabricated as a single MOS-LSI semiconductor chip and includes a large read-only-memory or ROM for storing instruction codes, along with addressing circuitry for generating addresses for the ROM by either sequencing a program counter or by branching to an address contained in a branch instruction code. At the same time as a branch instruction is implemented, parts of the instruction code used for the branch address may be employed as an op code to perform operations within the processor.
Inventors
- 👤 Graham S. Tubbs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:01
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/02; G06F9/00; G06F9/06; G06F9/22; G06F9/226
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
174 words
An electronic digital processor fabricated in a single LSI semiconductor device, including a large read-only-memory for storing instruction codes of word length of N bits, addressing circuitry for generating addresses having a given number of bits greater than N/2 for the read-only-memory by either sequencing a program counter when a branch instruction is not present or by branching to an address contained in a branch instruction code when present, the processor including an arithmetic unit having an input, a data memory having an output, and logic means responsive to an opcode for controlling transfer of data from the output of said data memory to the input of the arithmetic unit the improvement comprising means for generating an opcode at the same time that a branch instruction code is executed in the addressing circuitry, wherein parts of the branch instruction code used for the branch address also function as said opcode thereby causing data to be transferred from the output of the data memory to the input of the arithmetic unit by said logic means.
Claim 2
Dependent Claim
174 words
An electronic digital processor fabricated in a single LSI semiconductor device, including a large read-only-memory for storing instruction codes of word length of N bits, addressing circuitry for generating addresses having a given number of bits greater than N/2 for the read-only-memory by either sequencing a program counter when a branch instruction is not present or by branching to an address contained in a branch instruction code when present, the processor including an arithmetic unit having an input, a data memory having an output, and logic means responsive to an opcode for controlling transfer of data from the output of said data memory to the input of the arithmetic unit the improvement comprising means for generating an opcode at the same time that a branch instruction code is executed in the addressing circuitry, wherein parts of the branch instruction code used for the branch address also function as said opcode thereby causing data to be transferred from the output of the data memory to the input of the arithmetic unit by said logic means.
Claim 3
Dependent Claim
33 words
An electronic digital processor system according to claim 1, wherein means are provided to produce a carry function from the arithmetic unit by said opcode during the execution of the branch instruction code.
Claim 4
Dependent Claim
30 words
An electronic digital processor system according to claim 1, wherein the addressing circuitry selects a specific instruction in the instruction memory and means are provided for decoding the specific instruction.
Claim 5
Dependent Claim
38 words
An electronic digital processor system according to claim 3 including a branch latch and means to set the branch latch, wherein a first instruction sets the branch latch prior to execution of the instruction which generates the opcode.
Claim 6
Dependent Claim
57 words
An electronic digital processor system according to claim 4 wherein the branch latch produces an output indication, and a selector circuit in response to said indication generates an instruction word the same as the instruction word from the read-only-memory except for one bit for decoding and execution at substantially the same time as the branch instruction code.
Claim 7
Dependent Claim
23 words
An electronic digital processor system according to claim 5 wherein a decoder is provided which is responsive to instruction words to generate commands.
Claim 8
Dependent Claim
32 words
An electronic digital processor system according to claim 6 wherein the instruction generated in the selector circuit is applied to the decoder at substantially the same time as the branch instruction code.
Claim 9
Dependent Claim
49 words
An electronic digital processor system according to claim 7 wherein the decoder receives a part of each instruction word from the read-only-memory, except branch instructions, and receives part of the branch instructions when the branch latch is set during the instruction following the instruction which sets the branch latch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |