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US4072939A
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Analog-to-digital and digital-to-analog converter circuits employing charge redistribution
Assignee: International Business Machines Corp
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Filing: 1976-03-01
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Granted: 1978-02-07
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Expires: 1996-03-01
Abstract
Abstract Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet Q R is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value Q R /2, Q R /4, Q R /8, Q R /16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence Q R /2, Q R /2±Q R /4, Q R /2±Q R /4±Q R /8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum.
Inventors
- 👤 Lawrence G. Heller
- 👤 Lewis M. Terman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:16
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/472; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/46
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
441 words
An analog-to-digital converter circuit of the type employing successive approximation binary search techniques comprising: a source of analog input signal, a sequence generating circuit for generating a binarily decreasing sequence of electrical charge quantities of the form Q = Q R /2, Q R /4, Q R /8 up to Q R /2.sup. N where Q R is a predetermined quantity of electrical charge and N is a positive integer, a first storage means for sequentially accumulating a first plurality of first selected ones of said charge quantities from said sequence of electrical charge quantities. a second storage means for storing said input analog signal and for sequentially accumulating and adding to said analog signal a second plurality of other selected ones of said charge quantities from said sequence of electrical charge quantities, and means including an electrical charge diverting means, a comparator circuit and a logic control means connected to said sequence generating circuit, and said first and second storage means for sequentially comparing said accumulated charge quantities in said first and second storage means and for directing said charge quantities to said first and second storage means in accordance with said comparisons to produce an output signal representative of said comparisons, said logic control means being responsive to the output of said comparison means to provide an input signal to said diverting means such that when a comparison between the quantity stored in said first electrical charge storage means and the quantity stored in said second electrical charge storage means indicates that the quantity stored in said first electrical charge storage means is greater than the quantity stored in said second electrical charge storage means, a "0" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said second electrical charge storage means for addition to the quantity stored therein, and that when a comparison between the quantities stored in said first and second electrical charge storage means indicates that the quantity stored in said second electrical charge storage means is greater than the quantity stored in said first electrical charge storage means, a "1" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said first electrical charge storage means for addition to the quantity stored therein, said comparison, diverting and storage operations continuing for N occurrences, where N is said positive integer, to provide an N bit digital signal representative of said input analog signal.
Claim 2
Dependent Claim
441 words
An analog-to-digital converter circuit of the type employing successive approximation binary search techniques comprising: a source of analog input signal, a sequence generating circuit for generating a binarily decreasing sequence of electrical charge quantities of the form Q = Q R /2, Q R /4, Q R /8 up to Q R /2.sup. N where Q R is a predetermined quantity of electrical charge and N is a positive integer, a first storage means for sequentially accumulating a first plurality of first selected ones of said charge quantities from said sequence of electrical charge quantities. a second storage means for storing said input analog signal and for sequentially accumulating and adding to said analog signal a second plurality of other selected ones of said charge quantities from said sequence of electrical charge quantities, and means including an electrical charge diverting means, a comparator circuit and a logic control means connected to said sequence generating circuit, and said first and second storage means for sequentially comparing said accumulated charge quantities in said first and second storage means and for directing said charge quantities to said first and second storage means in accordance with said comparisons to produce an output signal representative of said comparisons, said logic control means being responsive to the output of said comparison means to provide an input signal to said diverting means such that when a comparison between the quantity stored in said first electrical charge storage means and the quantity stored in said second electrical charge storage means indicates that the quantity stored in said first electrical charge storage means is greater than the quantity stored in said second electrical charge storage means, a "0" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said second electrical charge storage means for addition to the quantity stored therein, and that when a comparison between the quantities stored in said first and second electrical charge storage means indicates that the quantity stored in said second electrical charge storage means is greater than the quantity stored in said first electrical charge storage means, a "1" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said first electrical charge storage means for addition to the quantity stored therein, said comparison, diverting and storage operations continuing for N occurrences, where N is said positive integer, to provide an N bit digital signal representative of said input analog signal.
Claim 3
Dependent Claim
103 words
A generating circuit according to claim 1 wherein said first and second charge carrier storage means includes a semiconductor substrate, a first storage electrode coupled to said semiconductor substrate for forming a first potential well for storing charge carriers in said substrate, a second storage electrode coupled to said semiconductor substrate for forming a second potential well for storing charge carriers in said substrate, and wherein said charge carrier transfer means includes a transfer electrode coupled to said substrate and disposed between said first and second storage electrodes for transferring said selected amounts of charge carriers between said first and second potential wells.
Claim 4
Dependent Claim
696 words
An analog-to-digital converter circuit of the type employing successive approximation binary search techniques comprising: a source of analog input signal, a circuit for generating a binarily decreasing sequence of electrical signal quantities including a first electrical charge storage means adapted to store up to a predetermined quantity of electrical charge Q R , a second electrical charge storage means also adapted to store up to said predetermined quantity of electrical charge Q R , and an electrical charge transfer means associated with said first and second electrical charge storage means for transferring from said first storage means to said second storage means and from said second storage means to said first storage means any selected amount of electrical charge of said predetermined quantity of electrical charge Q R for producing a binarily decreasing sequence of electrical charge quantities from said sequence generating means of the form Q=Q R /2, Q R /4, Q R /8 up to Q R /2.sup. N where N is a positive integer, a third electrical charge storage means for accumulating selected ones of said electrical charge quantities from said sequence generating circuit, a fourth electrical charge storage means for storing said input analog signal and for adding other selected ones of said electrical charge quantities from said sequence generator to said input analog signal, an electrical charge diverting means connected between said sequence generating circuit and said third and fourth storage means for directing first selected ones of said sequence of electrical charge quantities from said sequence generating circuit to said third storage means and other selected ones of said sequence of electrical charge quantities from said sequence generating circuit to said fourth storage means, said first selected ones of said sequence of electrical charge quantities being accumulated at said third electrical charge storage means and said other selected ones of said sequence of electrical charge quantities being accumulated and added to said input analog signal at said fourth electrical charge storage means to sequentially produce two separate accumulated quantities of electrical charge quantities, a comparator circuit having a first input terminal connected to said third electrical charge storage means and a second input terminal connected to said fourth electrical charge storage means for comparing the accumulated electrical charge in each of said third and fourth storage means and a logic control means connected between the output of said comparator circuit and to said electrical charge diverting means for controlling said electrical charge diverting means for directing said first selected electrical charge quantities and said other selected electrical charge quantities of said binarily decreasing sequence of electrical charge quantities from said sequence generating circuit selectively to said third and fourth storage means as a result of said compared accumulation of said comparator circuit, said logic control means being responsive to the output of said comparison means to provide an input signal to said diverting means such that when a comparison between the quantity stored in said third electrical charge storage means and the quantity stored in said fourth electrical charge storage means indicates that the quantity stored in said third electrical charge storage means is greater than the quantity stored in said fourth electrical charge storage means, a "0" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said fourth electrical charge storage means for addition to the quantity stored therein, and that when a comparison between the quantities stored in said third and fourth electrical charge storage means indicates that the quantity stored in said fourth electrical charge storage means is greater than the quantity stored in said third electrical charge storage means, a "1" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said third electrical charge storage means for addition to the quantity stored therein, said comparison, diverting and storage operations continuing for N occurrences, where N is said positive integer, to provide an N bit digital signal representative of said input analog signal.
Claim 5
Dependent Claim
696 words
An analog-to-digital converter circuit of the type employing successive approximation binary search techniques comprising: a source of analog input signal, a circuit for generating a binarily decreasing sequence of electrical signal quantities including a first electrical charge storage means adapted to store up to a predetermined quantity of electrical charge Q R , a second electrical charge storage means also adapted to store up to said predetermined quantity of electrical charge Q R , and an electrical charge transfer means associated with said first and second electrical charge storage means for transferring from said first storage means to said second storage means and from said second storage means to said first storage means any selected amount of electrical charge of said predetermined quantity of electrical charge Q R for producing a binarily decreasing sequence of electrical charge quantities from said sequence generating means of the form Q=Q R /2, Q R /4, Q R /8 up to Q R /2.sup. N where N is a positive integer, a third electrical charge storage means for accumulating selected ones of said electrical charge quantities from said sequence generating circuit, a fourth electrical charge storage means for storing said input analog signal and for adding other selected ones of said electrical charge quantities from said sequence generator to said input analog signal, an electrical charge diverting means connected between said sequence generating circuit and said third and fourth storage means for directing first selected ones of said sequence of electrical charge quantities from said sequence generating circuit to said third storage means and other selected ones of said sequence of electrical charge quantities from said sequence generating circuit to said fourth storage means, said first selected ones of said sequence of electrical charge quantities being accumulated at said third electrical charge storage means and said other selected ones of said sequence of electrical charge quantities being accumulated and added to said input analog signal at said fourth electrical charge storage means to sequentially produce two separate accumulated quantities of electrical charge quantities, a comparator circuit having a first input terminal connected to said third electrical charge storage means and a second input terminal connected to said fourth electrical charge storage means for comparing the accumulated electrical charge in each of said third and fourth storage means and a logic control means connected between the output of said comparator circuit and to said electrical charge diverting means for controlling said electrical charge diverting means for directing said first selected electrical charge quantities and said other selected electrical charge quantities of said binarily decreasing sequence of electrical charge quantities from said sequence generating circuit selectively to said third and fourth storage means as a result of said compared accumulation of said comparator circuit, said logic control means being responsive to the output of said comparison means to provide an input signal to said diverting means such that when a comparison between the quantity stored in said third electrical charge storage means and the quantity stored in said fourth electrical charge storage means indicates that the quantity stored in said third electrical charge storage means is greater than the quantity stored in said fourth electrical charge storage means, a "0" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said fourth electrical charge storage means for addition to the quantity stored therein, and that when a comparison between the quantities stored in said third and fourth electrical charge storage means indicates that the quantity stored in said fourth electrical charge storage means is greater than the quantity stored in said third electrical charge storage means, a "1" binary value is manifested and said logic control means controls said electrical charge diverting means to direct the next successive one of said binarily decreasing sequence of electrical charge quantities to said third electrical charge storage means for addition to the quantity stored therein, said comparison, diverting and storage operations continuing for N occurrences, where N is said positive integer, to provide an N bit digital signal representative of said input analog signal.
Claim 6
Dependent Claim
104 words
An analog-to-digital converter circuit according to claim 3 wherein said first and second charge carrier storage means includes a semiconductor substrate, a first storage electrode coupled to said semiconductor substrate for forming a first potential well for storing charge carriers in said substrate, a second storage electrode coupled to said semiconductor substrate for forming a second potential well for storing charge carriers in said substrate, and wherein said charge carrier transfer means includes a transfer electrode coupled to said substrate and disposed between said first and second storage electrodes for transferring said selected amounts of charge carriers between said first and second potential wells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |