US4072904A
Expired / Lapsed
US
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Presettable rate multiplier
Assignee: United States Department of the Navy
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Filing: 1976-09-23
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Granted: 1978-02-07
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Expires: 1996-09-23
Abstract
Abstract The present invention relates to a logic circuit design for shortening theime required to perform a rate multiplier function. The invention is readily adaptable to multi-channel applications.
Inventors
- 👤 Paul G. Casner
- 👤 Edward J. McDevitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:49
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H03K21/00; H03K21/08; H03K21/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
131 words
A rate multiplier, having a plurality of ordered rate inputs and a clock input, for generating an output frequency f out which is a fraction of an input frequency f in , comprising: a series of connected counting stages, each counting stage being clocked by the input clock and having a preset input which, when enabled, locks the counting stage into a given output state which inhibits the counting stage from counting when clocked, and logic circuit means, having the ordered rate inputs as inputs and having outputs connected to the series of connected counting stages, for controlling the enabling of the preset input of each counting stage so that no preset input can be enabled unless the preset inputs of all previous counting stages in the series are also enabled.
Claim 2
Dependent Claim
131 words
A rate multiplier, having a plurality of ordered rate inputs and a clock input, for generating an output frequency f out which is a fraction of an input frequency f in , comprising: a series of connected counting stages, each counting stage being clocked by the input clock and having a preset input which, when enabled, locks the counting stage into a given output state which inhibits the counting stage from counting when clocked, and logic circuit means, having the ordered rate inputs as inputs and having outputs connected to the series of connected counting stages, for controlling the enabling of the preset input of each counting stage so that no preset input can be enabled unless the preset inputs of all previous counting stages in the series are also enabled.
Claim 3
Dependent Claim
55 words
A rate multiplier as in claim 1, further comprising: a CLEAR input for initializing the output of all counting stages and an END OF MULTIPLICATION output connected to the output of the last counting stage, the END OF MULTIPLICATION output being produced when the last counting stage switches from one predetermined state to the other.
Claim 4
Dependent Claim
45 words
A rate multiplier as in claim 1 wherein the logic circuit means comprises: first inverter means connected to invert each, but the lowest order, rate input and means for ANDing the inverted rate input of a given stage with all higher order inverted rate inputs.
Claim 5
Dependent Claim
46 words
A rate multiplier as in claim 3, wherein each, but the lowest order, rate input is inverted and then ANDED with all higher order rate inputs, in the logic circuit means, the ANDED output representing the value of the preset input of a corresponding counting stage.
Claim 6
Dependent Claim
41 words
A rate multiplier as in claim 1, wherein, each rate input is connected to a corresponding preset input through the logic circuit means, where the higher the order of the rate input the earilier in the series the corresponding counting stage.
Claim 7
Dependent Claim
75 words
A rate multiplier as in claim 5, wherein the order of the rate inputs is defined by the term M' = F'·2.sup.(n'-1) +E'·2.sup.(n'-2) +. . . +A'·2.sup.O where F', E', . . . , and A' are rate inputs of decreasing order and M' represents the number of output pulses produced in response to N' pulses from the clock input and where N' = 2 n' where n' represents the number of non-preset counting stages.
Claim 8
Dependent Claim
41 words
A rate multiplier as in claim 5, further comprising: an output and a complement output from each counting stage, and gating circuitry for logically combining each rate input with selected outputs and complement outputs from the plurality of counting stages. pg,16
Claim 9
Dependent Claim
40 words
A rate multiplier as in claim 7, wherein each rate input is gated with both the complement output of the counting stage having the preset input corresponding to the rate input and the outputs of all less significant counting stages.
Claim 10
Dependent Claim
54 words
A rate multiplier as in claim 5, further comprising: a plurality of channels each having a rate input equal in order to a rate input in each of the other channels, and gate means for logically ANDing all rate inputs of equal order, the gate means output being entered into one corresponding preset input.
Claim 11
Dependent Claim
20 words
A rate multiplier as in claim 9, wherein a separate f out is generated for each channel of rate inputs.
Claim 12
Dependent Claim
75 words
A rate multiplier as in claim 10, further comprising a plurality of rate input channels, each channel having rate inputs of the same order wherein the inverted rate inputs of the same order generated in each channel are ANDed in the ANDing means together with the higher order rate inputs of all the channels after which the ANDing means output signal is fed into the preset input corresponding to the order of the rate input.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |