Patent US4071774A successfully refreshed from Google Patents.
US4071774A
Expired / Lapsed
US
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Integrated injection logic with both fan in and fan out Schottky diodes, serially connected between stages
Assignee: Toshiba Corp
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Filing: 1975-12-24
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Granted: 1978-01-31
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Expires: 1995-12-24
Abstract
Abstract In the semiconductor device, a P - conductivity type semiconductor layer is formed on an N + conductivity type semiconductor substrate by vapor phase growth technique, and a first N conductivity type region is formed in the P - conductivity type layer by diffusion to extend into the N + conductivity type substrate and to surround a portion of the P - conductivity type semiconductor layer thereby isolating that portion from the remainder. A second conductivity type region is formed in the first region by diffusion and a third N conductivity type region is formed on the isolated region of the P - conductivity type layer. At least one metal region is bonded to the isolated region and at least one metal region is bonded to the third region to form respective metal-semiconductor contact diodes. The second region, the first region and the P - conductivity type layer constitute a lateral PNP transistor while the third region, the P - conductivity type semiconductor layer and the N + conductivity type semiconductor substrate constitute a vertical NPN transistor.
Inventors
- 👤 Yukuya Tokumaru
- 👤 Masanori Nakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:58
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
106 words
A semiconductor circuit having a plurality of stages, each stage comprising at least one output terminal, at least one input terminal, a first transistor having an emitter connected to a power source, and collector connected to said input terminal through a first diode and a second transistor having conductivity type opposite to that of said first transistor and including an emitter and base respectively connected to the base and collector of said first transistor and at least one collector connected to said output terminal through a second diode, the output terminal of one of said stages being connected to the input terminal of a succeeding stage.
Claim 2
Dependent Claim
106 words
A semiconductor circuit having a plurality of stages, each stage comprising at least one output terminal, at least one input terminal, a first transistor having an emitter connected to a power source, and collector connected to said input terminal through a first diode and a second transistor having conductivity type opposite to that of said first transistor and including an emitter and base respectively connected to the base and collector of said first transistor and at least one collector connected to said output terminal through a second diode, the output terminal of one of said stages being connected to the input terminal of a succeeding stage.
Claim 3
Dependent Claim
49 words
A semiconductor circuit according to claim 1 wherein said first transistor comprises a PNP transistor, said second transistor comprises an NPN transistor, the cathode electrode of said first diode is connected to said input terminal and the anode electrode of said second diode is connected to the output terminal.
Claim 4
Dependent Claim
201 words
A semiconductor device comprising a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type and formed on said semiconductor substrate, a first region of said one conductivity type extending into said semiconductor substrate to surround a portion of said semiconductor layer thereby defining an isolated region of the opposite conductivity type, a second region of the opposite conductivity type formed in said first region, at least one third region of said conductivity type formed in one surface of said isolated region, at least one metal region bonded to said third region to form a Schottky barrier diode therebetween, and at least one second metal region bonded to said isolated region to form a Schottky barrier diode therebetween, wherein said second region, said first region and said isolated region constitute a first transistor, and said third region, said isolated region and said semiconductor substrate constitute a second transistor, and the sum of the forward voltages of the Schottky diode formed between said first metal region and said third region and that formed between said second metal region and said semiconductor layer is lower than the forward voltage at the junction between said substrate and said isolated region.
Claim 5
Dependent Claim
201 words
A semiconductor device comprising a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type and formed on said semiconductor substrate, a first region of said one conductivity type extending into said semiconductor substrate to surround a portion of said semiconductor layer thereby defining an isolated region of the opposite conductivity type, a second region of the opposite conductivity type formed in said first region, at least one third region of said conductivity type formed in one surface of said isolated region, at least one metal region bonded to said third region to form a Schottky barrier diode therebetween, and at least one second metal region bonded to said isolated region to form a Schottky barrier diode therebetween, wherein said second region, said first region and said isolated region constitute a first transistor, and said third region, said isolated region and said semiconductor substrate constitute a second transistor, and the sum of the forward voltages of the Schottky diode formed between said first metal region and said third region and that formed between said second metal region and said semiconductor layer is lower than the forward voltage at the junction between said substrate and said isolated region.
Claim 6
Dependent Claim
27 words
A semiconductor device according to claim 3 wherein said one conductivity type is of the N type and said opposite conductivity type is of the P type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-30 | 1981-08-01 | 1982-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-30 | 1985-08-01 | 1986-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-30 | 1989-08-01 | 1990-01-31 | $7700.00 | Window Closed / Lapsed |