US4071706A
Expired / Lapsed
US
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Data packets distribution loop
Assignee: RCA Corp
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Filing: 1976-09-13
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Granted: 1978-01-31
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Expires: 1996-09-13
Abstract
Abstract A data communications or distribution loop has a plurality of computer stations each of which introduces a delay while it examines the header of each circulating packet or block of data. An elastic synchronizing buffer, including a random-access memory, is included in the loop to introduce a delay which, when added to the delays introduced by the stations, equals the period of a packet. The delay introduced by the buffer is automatically adjusted as stations are added to, or removed from, the loop.
Inventors
- 👤 Charles Stewart Warren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4247; H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/422
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
177 words
A synchronizer for inclusion in a data communications system loop in which packets of N information bits circulate together with clock pulses and packet-start pulses in a loop having S stations each of which introduces a delay corresponding with the time of n clock pulses, comprising a random access memory, an input address counter means counting to N, incremented by each clock pulse and reset by each packet-start pulse, to store successive information bits in successive memory locations, and an output address counter means, incremented by each clock pulse and reset upon reaching a count equal to the number N of bits in the packet, to read out information bits successively from successive memory locations, whereby the contents of said address counters differ by an amount d so that the memory introduces a delay equal to d clock pulses, which, when added to the number n times S of clock pulse delays introduced by the S stations connected in the loop, is an integral multiple, including unity, of the number of N of bits in each packet.
Claim 2
Dependent Claim
177 words
A synchronizer for inclusion in a data communications system loop in which packets of N information bits circulate together with clock pulses and packet-start pulses in a loop having S stations each of which introduces a delay corresponding with the time of n clock pulses, comprising a random access memory, an input address counter means counting to N, incremented by each clock pulse and reset by each packet-start pulse, to store successive information bits in successive memory locations, and an output address counter means, incremented by each clock pulse and reset upon reaching a count equal to the number N of bits in the packet, to read out information bits successively from successive memory locations, whereby the contents of said address counters differ by an amount d so that the memory introduces a delay equal to d clock pulses, which, when added to the number n times S of clock pulse delays introduced by the S stations connected in the loop, is an integral multiple, including unity, of the number of N of bits in each packet.
Claim 3
Dependent Claim
23 words
A synchronizer according to claim 1 including means operative upon each said resetting of said output address counter to transmit a packet-start pulse.
Claim 4
Dependent Claim
36 words
A synchronizer according to claim 1 including means operative upon each said resetting of said output address counter, if no packet-start pulse was received since the last resetting of the counter, to transmit an empty packet.
Claim 5
Dependent Claim
41 words
A synchronizer according to claim 1 including means operative upon each setting of said output address counter, if no packet-start pulse was received since the last resetting of the counter, to transmit a packet header signifying that the packet is empty.
Claim 6
Dependent Claim
28 words
A synchronizer according to claim 1 including means operative between two predetermined counts of said output address counter to transmit guard bits between information bits of successive packets.
Claim 7
Dependent Claim
159 words
A data loop communications system, comprising a plurality of stations connected in a loop through which packets of information bits circulate together with clock pulses and packet-start pulses, each of said stations introducing a delay, and a synchronizer connected in the communications system loop and including a random access memory an input address counter means counting to N, incremented by each clock pulse and reset by each packet start pulse, to store successive information bits in successive memory locations, and an output address counter means, incremented by each clock pulse and reset upon reaching a count equal to the number of bits in the packet, to read out information bits successively from successive memory locations, whereby the contents of said address counters differ by an amount such that the memory introduces a delay, which, when added to the delays introduced by the stations connected in the loop, is an integral multiple, including unity, of the period of a packet.
Claim 8
Dependent Claim
159 words
A data loop communications system, comprising a plurality of stations connected in a loop through which packets of information bits circulate together with clock pulses and packet-start pulses, each of said stations introducing a delay, and a synchronizer connected in the communications system loop and including a random access memory an input address counter means counting to N, incremented by each clock pulse and reset by each packet start pulse, to store successive information bits in successive memory locations, and an output address counter means, incremented by each clock pulse and reset upon reaching a count equal to the number of bits in the packet, to read out information bits successively from successive memory locations, whereby the contents of said address counters differ by an amount such that the memory introduces a delay, which, when added to the delays introduced by the stations connected in the loop, is an integral multiple, including unity, of the period of a packet.
Claim 9
Dependent Claim
27 words
A system according to claim 6 in which said synchronizer includes means operative upon each said resetting of said output address counter to transmit a packet-start pulse.
Claim 10
Dependent Claim
40 words
A system according to claim 6 in which said synchronizer includes means operative upon each said resetting of said output address counter, if no packet-start pulse was received since the last resetting of the counter, to transmit an empty packet.
Claim 11
Dependent Claim
46 words
A system according to claim 6 in which said synchronizer includes means operative upon each setting of said output address counter, if no packet start pulse was received since the last resetting of the counter, to transmit a packet header signifying that the packet is empty.
Claim 12
Dependent Claim
32 words
A system according to claim 6, in which said synchronizer includes means operative between two predetermined counts of said output address counter to transmit guard bits between information bits of successive packets.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-30 | 1981-08-01 | 1982-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-30 | 1985-08-01 | 1986-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-30 | 1989-08-01 | 1990-01-31 | $7700.00 | Window Closed / Lapsed |