Dynamic logic system

Claim 1

In combination; a field effect transistor having a source, a drain and gate for providing an impedance condition between said source and said drain; a first controlled switch having a first control terminal and first and second controlled terminals, said switch being responsive to a signal applied to said control terminal for altering the impedance between said first and second controlled terminals; means for connecting said source and drain to said first and second controlled terminals providing first and second nodes, respectively; a second controlled switch having a second control terminal and third and fourth controlled terminals; means for connecting said second control terminal to said first node; a first capacitor having first and second electrodes; means for connecting said second node to said second electrode; means for providing a clock signal between said first electrode and said first node; means for applying said clock signal to said first control terminal; means for applying an information signal to said third controlled terminal; a second capacitor connected between said first electrode of said first capacitor and said fourth controlled terminal; and means for connecting said fourth controlled terminal to said gate of said field effect transistor.