Semiconductor latch circuit using integrated logic units and Schottky diode in combination

Claim 1

A semiconductor latch circuit operative with a power source comprising a first integrated injection logic unit formed of a first switching transistor and a first injector transistor; a second integrated injection logic unit formed of a second switching transistor and a second injector transistor; an output signal leading-out transistor having first and second collectors; an input terminal for receiving a pulse signal to be latched; a first Schottky diode connected between the base of the first switching transistor and said input terminal; strobe signal input means operatively connected to the respective bases of said first and second switching transistors for providing strobe signals thereto; an output terminal connected to the first collector of the output signal leading-out transistor; wherein the emitters of the first and second injector transistors are connected to the power source; the collector of the first injector transistor and the collector of the second injector transistor are connected to the bases of the first and second switching transistors, respectively; the bases of the first and second injector transistors are connected to a reference potential; the collectors of the first and second switching transistors are connected to the base of the output signa leading-out transistor; the emitters of the first and second switching transistors are connected to the reference potential; the second collector of the output signal leading-out transistor is connected to the base of the second switching transistor; and said first Schottky diode is rendered nonconductive when a pulse signal supplied to the pulse signal input terminal has a level of "1".