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US4064554A
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Microcomputer with code conversion
Assignee: Texas Instruments Inc
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Filing: 1976-08-16
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Granted: 1977-12-20
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Expires: 1996-08-16
Abstract
Abstract An electronic digital processor which may be used in a hand-held calculator is implemented in a single MOS/LSI semiconductor chip. The processor includes a ROM for storing instruction codes, a RAM for storing data, an arithmetic unit for performing operations on data under control of micro-instructions or commands, and control circuitry including a decoder for generating the commands in response to the instruction codes. The arithmetic unit is controlled by a group of micro-instructions generated from a certain class of instruction codes, while another class of instruction codes includes fields for constants used in some operations such as "compare contents of accumulator with a constant." The class of instructions for controlling the arithmetic unit is directly coupled to a decoder for generating the microinstructions, while the class containing constants is "faked" or indirectly coupled to the decoder through a converter which changes the instruction codes to resemble the ones which control the arithmetic unit. Some of the bit positions which define the constant may, through conversion, be used to generate microinstructions. This arrangement is more efficient in utilization of space on the chip, for a given instruction set.
Inventors
- 👤 Graham S. Tubbs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:21
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/226; G06F15/00; G06F15/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
257 words
A digital processor of the type having: instruction word access means for producing instruction words on a plurality of parallel output lines; an arithmetic unit having inputs and outputs and control signal input means for receiving controls for defining the operation thereof; data storage means having input control means and output control means for defining store and recall of data therein, the data storage means having data outputs interconnected by coupling means with inputs of the arithmetic logic unit and having data inputs interconnected by coupling means with outputs of the arithmetic logic unit; control means including decoder means connected to receive instruction words from the plurality of parallel output lines and operative to produce control signals for defining the operation of the arithmetic unit and the coupling means and for defining store and recall of data in the data storage means via said input control means and output control means; the improvement wherein the control means comprises: first connection means for applying certain instructions from the plurality of parallel outputs in non-modified form to the decoder means, logic means responsive to the contents of the instruction words included in the first connection means for completing the connection; second connection means for applying other selected instructions from the plurality of parallel inputs to the decoder means in a modified form, conversion means included in the second connection means to change the logical content of parts of the instruction words in the other selected instructions to correspond to the contents of the instruction words of said certain instructions.
Claim 2
Dependent Claim
257 words
A digital processor of the type having: instruction word access means for producing instruction words on a plurality of parallel output lines; an arithmetic unit having inputs and outputs and control signal input means for receiving controls for defining the operation thereof; data storage means having input control means and output control means for defining store and recall of data therein, the data storage means having data outputs interconnected by coupling means with inputs of the arithmetic logic unit and having data inputs interconnected by coupling means with outputs of the arithmetic logic unit; control means including decoder means connected to receive instruction words from the plurality of parallel output lines and operative to produce control signals for defining the operation of the arithmetic unit and the coupling means and for defining store and recall of data in the data storage means via said input control means and output control means; the improvement wherein the control means comprises: first connection means for applying certain instructions from the plurality of parallel outputs in non-modified form to the decoder means, logic means responsive to the contents of the instruction words included in the first connection means for completing the connection; second connection means for applying other selected instructions from the plurality of parallel inputs to the decoder means in a modified form, conversion means included in the second connection means to change the logical content of parts of the instruction words in the other selected instructions to correspond to the contents of the instruction words of said certain instructions.
Claim 3
Dependent Claim
30 words
A digital processor according to claim 1 wherein the instruction word access means is addressable, and addressing means are included for applying an address to the instruction word access means.
Claim 4
Dependent Claim
29 words
A digital processor according to claim 2 wherein the first connection means includes means for applying a given type of instructions to the addressing means to provide branch operations.
Claim 5
Dependent Claim
52 words
A digital processor according to claim 3 wherein the logic means of the first connection means includes means responsive to said certain instructions and the instructions of a given type for completing the connection in non-modified form and includes means responsive to the other selected instructions for preventing completion of such connection.
Claim 6
Dependent Claim
30 words
A digital processor according to claim 1 wherein the other selected instructions includes a multiple-bit part thereof which is connected via said coupling means to inputs of the arithmetic unit.
Claim 7
Dependent Claim
51 words
A digital processor according to claim 5 wherein the instruction words each contain a plurality of bits, a first set of which in other selected instructions is the multi-bit part, and a second set of which in the other selected instructions is the opcode, the second set overlapping the first set.
Claim 8
Dependent Claim
27 words
A digital processor according to claim 1 wherein the instruction word access means includes a read-only-memory and addressing means for providing an address to the read-only memory.
Claim 9
Dependent Claim
29 words
A digital processor according to claim 7 wherein the processor is a single semiconductor integrated circuit chip and the read-only-memory and decoder means comprise MOS transistors mask-programmable in manufacture.
Claim 10
Dependent Claim
42 words
A digital processor according to claim 1 wherein the conversion means includes means to change said parts of the instruction words to resemble said certain instruction words, and the other selected instructions are also utilized in unchanged form to provide operation data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-19 | 1981-06-20 | 1981-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-19 | 1985-06-20 | 1985-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-19 | 1989-06-20 | 1989-12-20 | $7700.00 | Window Closed / Lapsed |