Patent US4064493A successfully refreshed from Google Patents.
US4064493A
Expired / Lapsed
US
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P-ROM Cell having a low current fusible programming link
Assignee: Motorola Solutions Inc
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Filing: 1976-06-03
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Granted: 1977-12-20
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Expires: 1996-06-03
Abstract
Abstract A programmable cell for a P-ROM (programmable read only memory) matrix includes a bipolar transistor having a fusible link in one of the transistor leads on the substrate. The fusible link is a "necked-down" portion of one of the leads, positioned adjacent the base-collector junction where it is heated by the junction current, causing the links to open at a low fusing current.
Inventors
- 👤 Walter Lee Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:57
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
84 words
A permanently alterable semiconductor cell comprising at least a transistor and a fusible elements, the fusible element being coupled in series with an element of said transistor for being fused by a predetermined current through said transistor, said predetermined current being substantially greater than the normal operating current of said transistor, the fusible element being positioned for receiving thermal energy from a junction region of said transistor whereby the predetermined current required for fusing the element is substantially reduced due to said thermal energy.
Claim 2
Dependent Claim
84 words
A permanently alterable semiconductor cell comprising at least a transistor and a fusible elements, the fusible element being coupled in series with an element of said transistor for being fused by a predetermined current through said transistor, said predetermined current being substantially greater than the normal operating current of said transistor, the fusible element being positioned for receiving thermal energy from a junction region of said transistor whereby the predetermined current required for fusing the element is substantially reduced due to said thermal energy.
Claim 3
Dependent Claim
23 words
A permanently alterable semiconductor cell according to claim 1 wherein the fusible element forms a portion of the emitter lead of said transistor.
Claim 4
Dependent Claim
23 words
A permanently alterable semiconductor cell according to claim 1 wherein the fusible element forms a portion of the collector lead of said transistor.
Claim 5
Dependent Claim
29 words
A permanently alterable semiconductor cell according to claim 1 wherein the transistor lead is a deposited aluminum layer and the fusible element comprises a narrowed portion of said layer.
Claim 6
Dependent Claim
20 words
A permanently alterable semiconductor cell according to claim 1 wherein said junction region of the transistor comprises the collector-base junction.
Claim 7
Dependent Claim
100 words
An integrated circuit programmable read only memory comprising: a plurality of cells interconnected to form an array of rows and columns, each cell containing at least a transistor and a fusible element, said fusible element coupled in series with an element of said transistor for being fused by a predetermined current through said transistor, said predetermined current being substantially greater than the normal operating current of said transistor, the fusible element positioned for receiving thermal energy from a junction region of said transistor, whereby the predetermined current required for fusing the element is substantially reduced due to said thermal energy.
Claim 8
Dependent Claim
100 words
An integrated circuit programmable read only memory comprising: a plurality of cells interconnected to form an array of rows and columns, each cell containing at least a transistor and a fusible element, said fusible element coupled in series with an element of said transistor for being fused by a predetermined current through said transistor, said predetermined current being substantially greater than the normal operating current of said transistor, the fusible element positioned for receiving thermal energy from a junction region of said transistor, whereby the predetermined current required for fusing the element is substantially reduced due to said thermal energy.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-19 | 1981-06-20 | 1981-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-19 | 1985-06-20 | 1985-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-19 | 1989-06-20 | 1989-12-20 | $7700.00 | Window Closed / Lapsed |