US3971058A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual emitter programmable memory element and matrix
Assignee: Intersil Corp
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Filing: 1974-01-07
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Granted: 1976-07-20
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Expires: 1994-01-07
Abstract
Abstract A plurality of dual emitter integrated circuit transistor elements in a single substrate having emitters interconnected to form a matrix is programmed by passing current between emitters of selected elements to short one base-emitter junction or to short one emitter to base and collector. A programmed ROM has a programmed bit electrically represented by a transistor and an unprogrammed location electrically represented by back-to-back transistors. Alternative programming of a bit or address may provide a diode connection for a programmed matrix bit and furthermore may provide an extremely short or low storage time for a programmed matrix bit diode.
Inventors
- 👤 Lloyd D. Fagan
- 👤 Gareth A. Tripp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:16
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10B; H10B69/00; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; Y; Y10; Y10S; Y10S257/00; Y10S257/926
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
142 words
An improved integrated circuit field programmable read only memory matrix comprising a plurality of dual emitter transistor elements disposed in a single substrate with each transistor having, a high conductivity burried collector region, a base region having no electrical contact thereto disposed above said burried collector region and having a PN junction therebetween, and a pair of separate emitter regions extending into said base region from an upper surface thereof, first electrical conductors connecting pluralities of first emitters of said transistors in separate rows; and second electrical conductors connecting pluralities of second emitters of said transistors in separate columns to form a matrix having a programmable address at each crossover of row and column whereby application of electrical power between a selected row and column to electrically short a base-emitter junction of an element connected therebetween programs an address of the matrix.
Claim 2
Dependent Claim
142 words
An improved integrated circuit field programmable read only memory matrix comprising a plurality of dual emitter transistor elements disposed in a single substrate with each transistor having, a high conductivity burried collector region, a base region having no electrical contact thereto disposed above said burried collector region and having a PN junction therebetween, and a pair of separate emitter regions extending into said base region from an upper surface thereof, first electrical conductors connecting pluralities of first emitters of said transistors in separate rows; and second electrical conductors connecting pluralities of second emitters of said transistors in separate columns to form a matrix having a programmable address at each crossover of row and column whereby application of electrical power between a selected row and column to electrically short a base-emitter junction of an element connected therebetween programs an address of the matrix.
Claim 3
Dependent Claim
30 words
The matrix of claim 1 further defined by each of said elements having a buried collector region and a base region disposed in an epitaxial layer over said collector region.
Claim 4
Dependent Claim
48 words
The matrix of claim 1 further defined by an insulating layer covering said elements and having openings therethrough to emitters of said elements, and said first and second conductors comprising metal conductors upon said insulating layer extending into ohmic contact with emitters through said openings in said layer.
Claim 5
Dependent Claim
112 words
An electrically programmable memory array comprising a plurality of transistors with each transistor having two separate emitter regions extending into the upper surface of a single base region having no electrical connection thereto and a high conductivity collector region below said base region with a PN junction therebetween, first electrical conductors connecting together the first emitters of said transistors in separate rows, and second electrical conductors connecting together second emitters of said transistors in separate columns, whereby said transistors are individually electrically programmable by the application of programming signals to a selected row and column to electrically short at least a base-emitter junction of the transistor connected to said row and column.
Claim 6
Dependent Claim
112 words
An electrically programmable memory array comprising a plurality of transistors with each transistor having two separate emitter regions extending into the upper surface of a single base region having no electrical connection thereto and a high conductivity collector region below said base region with a PN junction therebetween, first electrical conductors connecting together the first emitters of said transistors in separate rows, and second electrical conductors connecting together second emitters of said transistors in separate columns, whereby said transistors are individually electrically programmable by the application of programming signals to a selected row and column to electrically short at least a base-emitter junction of the transistor connected to said row and column.
Claim 7
Dependent Claim
154 words
A programmed memory matrix comprising a plurality of dual emitter transistors with each transistor having first and second emitter regions extending into the upper surface of a base region having no electrical connection thereto and a high conductivity collector region beneath said base region with a PN junction therebetween, a plurality of first conductors electrically connecting first emitters of said transistors in a plurality of separate rows, a plurality of second conductors electrically connecting second emitters of said transistors in a plurality of separate columns whereby said transistors each have an emitter connected in a row and an emitter connected in a column as a matrix crossover to electrically provide a pair of collector-connected transistors at each row and column crossover as a matrix address, and selected transistors having one electrically shorted emitter-base junction to electrically provide a diode and transistor connected in a series between row and column as a programmed matrix address.
Claim 8
Dependent Claim
154 words
A programmed memory matrix comprising a plurality of dual emitter transistors with each transistor having first and second emitter regions extending into the upper surface of a base region having no electrical connection thereto and a high conductivity collector region beneath said base region with a PN junction therebetween, a plurality of first conductors electrically connecting first emitters of said transistors in a plurality of separate rows, a plurality of second conductors electrically connecting second emitters of said transistors in a plurality of separate columns whereby said transistors each have an emitter connected in a row and an emitter connected in a column as a matrix crossover to electrically provide a pair of collector-connected transistors at each row and column crossover as a matrix address, and selected transistors having one electrically shorted emitter-base junction to electrically provide a diode and transistor connected in a series between row and column as a programmed matrix address.
Claim 9
Dependent Claim
46 words
The programmed memory matrix of claim 5 further defined by selected transistors having one emitter thereof electrically shorted to the transistor base and the transmitter base shorted to the collector thereof to electrically provide a diode connected between row and column as a programmed matrix address.
Claim 10
Independent Claim
167 words
A method of electrically programming a semiconductor memory matrix having a dual emitter transistor disposed at each row and column crossover with each transistor having a high conductivity collector region, a base region having no electrical contact thereto disposed above said collector region, and having a PN junction therebetween, and a pair of emitter regions extending into said base region from an upper surface thereof, and each transistor having a first emitter connected to one row and a second emitter connected to one column to provide a memory address and comprising the steps of electrically connecting a selected row and column of the matrix across a programming signal source to pass an electrical current between the emitters of the transistor at the crossover thereof, and applying sufficient power to said transistor from said programming signal source to electrically short a base-emitter junction of said transistor and form a programmed address as a crossover connection electrically comprising a transistor and diode connected in series between row and column.
Claim 11
Independent Claim
167 words
A method of electrically programming a semiconductor memory matrix having a dual emitter transistor disposed at each row and column crossover with each transistor having a high conductivity collector region, a base region having no electrical contact thereto disposed above said collector region, and having a PN junction therebetween, and a pair of emitter regions extending into said base region from an upper surface thereof, and each transistor having a first emitter connected to one row and a second emitter connected to one column to provide a memory address and comprising the steps of electrically connecting a selected row and column of the matrix across a programming signal source to pass an electrical current between the emitters of the transistor at the crossover thereof, and applying sufficient power to said transistor from said programming signal source to electrically short a base-emitter junction of said transistor and form a programmed address as a crossover connection electrically comprising a transistor and diode connected in series between row and column.
Claim 12
Dependent Claim
44 words
The method of programming as set forth in claim 7 further defined by applying additional electrical power from said programming signal source to electrically short said emitter to base and collector to form the programmed address as a diode connected between row and column.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-20 | 1980-01-19 | 1980-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-20 | 1984-01-19 | 1984-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-20 | 1988-01-19 | 1988-07-20 | $7700.00 | Window Closed / Lapsed |