Digital radar signal processor

Claim 2

A digital signal processor for use with a radar receiver, comprising: an adaptive constant false alarm threshold loop connected to receive signal returns from said radar receiver for producing a signal indicative of a target, memory means connected to receive said signal indicative of a target for storing said signal and updating said signal in accordance with successive signals indicative of a target and producing a digital word indicative of said target, an adaptive background average threshold loop connected to receive said digital word indicative of said target for comparing said word with selected words which precede and follow said word in time and for producing an output signal declaring a target if said word exceeds said selected words, a track signal processor having a first input connected to a track loop signal and a second input connected to receive said output signal from said adaptive background average threshold loop for providing digital range and velocity signals, and an error word generator connected to receive said digital range and velocity signals from said track signal processor for producing an error word signal which is fed back to said first input of said track signal processor for closing a track signal loop.

Claim 3

The digital signal processor of claim 1 wherein said adaptive constant false alarm threshold loop comprises: a threshold detector having a first input connected to receive said radar signal returns and a second input connected to receive a feedback signal from said adaptive constant false alarm threshold loop for producing a pulsed output signal indicative of a target if said signal at said first input exceeds said signal at said second input, noise gate signal generator means connected to said radar receiver for producing a gate pulse output signal during a dead period of said radar receiver, a false alarm counter having a first input connected to receive said output signal from said threshold detector and a second input connected to said gate pulse output signal for counting a number of pulses of said first input which occur within said gate of said second input and producing an output signal proportional to said number, and preset comparator means having an input connected to receive said output signal from said false alarm counter producing said feedback signal connected to said threshold detector when said output signal from said false alarm counter exceeds a preselected number.

Claim 4

The digital signal processor of claim 2 wherein said memory means comprises: first and second selectively enabled buffer shift register means connected to receive said pulsed output signal from said threshold detector and each producing an output signal, input word matrix means connected to said first and second shift register means for selectively enabling said first and second buffer shift register means, a memory portion having a first input connected to selectively receive the output from said first shift register and the output from said second shift register and a second input, channelled through said input word matrix means, connected to receive an updated digital word from a feedback loop for producing a binary word output indicating a number of target returns, and third shift register means connected to receive said binary word output from said memory means for producing said digital word indicative of said target and for being fed back to said second input of said memory means.

Claim 5

The digital signal processor of claim 3 wherein said adaptive background average threshold loop comprises: a slope sum unit connected to receive said digital word from said memory means for producing a digital sum of target detections along a certain slope for a certain range cell of said digital word, a background sum unit connected to receive said digital word for producing a digital sum of target detections along said certain slope for each of a plurality of range cells proximate to said certain range cell of said digital word, a parallel adder for producing a summed output of the target detections associated with all of said proximate range cells, comparator means, having a first input connected to receive said summed output signal from said parallel adder and a second input connected to receive said digital sum from said slope sum unit, for producing a target-declared output signal when said slope sum output signal exceeds said background sum output signal, and slope allow logic means, connected to receive target-declared output signals from said comparator means, for disallowing the transmitting to said track signal processor of certain target-declared output signals according to a pre-established priority scheme.

Claim 6

The digital signal processor of claim 4 wherein said track signal processor comprises: a first selectively enabled shift register connected to receive said output signal from said second threshold loop for producing an output signal representing a range word, a second selectively enabled shift register connected to receive said output signal from said second threshold loop for producing an output signal representing a velocity word, and an arithmetic unit having a first input connected to receive said signal representing a range word, a second input connected to receive said signal representing a velocity word, and a third input connected to receive said error word signal from said error word generator for adding or subtracting said third input to a corresponding one of said first and second inputs for producing an error adjusted range word output signal and an error adjusted velocity word output signal, respectively.

Claim 7

The digital signal processor of claim 5 wherein said error word generator comprises: a split-gate error detector connected to receive said digital range and velocity signals from said track signal processor for producing an output error signal therefrom, an analog to digital converter connected to receive said output error signal from said split gate error detector for producing a converted output signal, and a shift register connected to receive said converted output signal for producing said error word signal.

Claim 8

A signal processor for use with a radar receiver receiving signals containing noise pulses, said signal processor, comprising: constant false alarm rate averaging means connected to receive said radar signals from said receiver for counting said noise pulses occurring in a selected time period and producing an output n-word signal when said pulses exceed a selected number, memory means having a first input connected to receive said output n-word signals from said constant false alarm rate averaging means for storing and updating a selected number of said output n-word signals and producing an output signal when said selected number of n-word signals has been exceeded, slope summing means connected to receive said output signals from said memory means for producing a current slope summed output signal therefrom, background sum adder means connected to said slope summing means for combining prior and subsequent slope summed output signals and decoder means connected to said background sum adder means for generating a background sum-related threshold value, m, second threshold means having a first input connected to receive said current slope summed output signal from said slope summing means and a second input to receive said background sum-related threshold for producing an output m-word signal when said first input signal exceeds said second input signal, and tracking signal processing means connected to receive said output m-word signal from said second threshold means for correcting any errors contained in said output m-word signal.

Claim 9

A signal processor for use with a radar receiver receiving signals containing noise pulses, said signal processor, comprising: constant false alarm rate averaging means connected to receive said radar signals from said receiver for counting said noise pulses occurring in a selected time period and producing an output n-word signal when said pulses exceed a selected number, memory means having a first input connected to receive said output n-word signals from said constant false alarm rate averaging means for storing and updating a selected number of said output n-word signals and producing an output signal when said selected number of n-word signals has been exceeded, slope summing means connected to receive said output signals from said memory means for producing a current slope summed output signal therefrom, background sum adder means connected to said slope summing means for combining prior and subsequent slope summed output signals and decoder means connected to said background sum adder means for generating a background sum-related threshold value, m, second threshold means having a first input connected to receive said current slope summed output signal from said slope summing means and a second input to receive said background sum-related threshold for producing an output m-word signal when said first input signal exceeds said second input signal, and tracking signal processing means connected to receive said output m-word signal from said second threshold means for correcting any errors contained in said output m-word signal.

Claim 10

The signal processor of claim 7 wherein said constant false alarm rate averaging means comprises, a false alarm counter connected to receive actual false alarm count signals emanating from said receiver, an expected count unit for periodically generating an expected false alarm count established by external means, comparator means having a first input connected to receive actual false alarm count signals emanating from said false alarm counter and a second input connected to receive the output from said expected count unit for producing a threshold update signal when said first input differs from said second input, and a threshold storage register means receiving the comparator means output as its input for changing and storing an updated threshold value.

Claim 11

The signal processor of claim 8 wherein said tracking signal processing means for correcting any errors comprises: first and second shift register means each connected to receive said output m-word signal from said second threshold means for storing said output m-words and producing velocity and range output words, respectively, therefrom, split-gate error detector means connected to receive said output m-word signal for producing an error value from which velocity and range error output signals are derived, and arithmetic unit means having first input connected to receive said velocity output words from said first shift register means and a second input connected to receive said range output words from said second shift register and a third input connected to receive said velocity and range error output signals for adding said velocity error signals to said first input signals and said range error signals to said second input signals.