US3761922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital mean level detector
Assignee: Raytheon Co
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Filing: 1971-10-12
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Granted: 1973-09-25
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Expires: 1991-10-12
Abstract
Abstract A digital mean level detector that processes the digital radar data so that the mean or RMS noise level is accurately determined and selected offset threshold levels can be varied to provide highly accurate and reliable signal detection. The system first provides mean level detection of the digital input signal which is applied to a threshold compare circuit having a plurality of thresholds such as two, for example. The output signals of the threshold compare circuit are encoded and sent both to a delay register and to an accumulator, with the outputs of both being applied to a subtractor for eliminating the oldest signal of a moving window sum held in the accumulator. The signal at the output of the subtractor is applied to the accumulator where it is added to the present signal at the output of the threshold compare circuit. At each range bin, the accumulated sum is then compared with an expected count representing the mean level of the noise for the selected number of range bins. The difference, representative of a predetermined error of the input noise level, is then adjusted and used to correct a signal detector having an offset threshold as determined by selected detection codes.
Inventors
- 👤 N Evans
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:36
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/292; G01S7/2923; G01S7/2927
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
166 words
A detector responsive to a radar signal comprising analog-to-digital converter means responsive to said radar signal to develop a digital amplitude signal of a predetermined number of bits, amplitude limiting means coupled to said analog-to-digital converter means for passing a selected number of the least significant bits of said digital amplitude signal, threshold comparator means coupled to said amplitude limiting means and responsive to said digital amplitude signal, delay means responsive to said threshold comparator means, accumulator means responsive to said threshold comparator means, subtractor means responsive to said delay means and to said accumulator means, and coupled to an input of said accumulator means, dividing means coupled to the output of said accumulator means to provide a threshold error signal, and detector comparator means coupled to said dividing means for receiving said threshold error signal and responsive to said digital amplitude signal for detecting the occurrences of the value of said digital signal exceeding a controlled threshold value with a substantially constant false alarm rate.
Claim 2
Dependent Claim
166 words
A detector responsive to a radar signal comprising analog-to-digital converter means responsive to said radar signal to develop a digital amplitude signal of a predetermined number of bits, amplitude limiting means coupled to said analog-to-digital converter means for passing a selected number of the least significant bits of said digital amplitude signal, threshold comparator means coupled to said amplitude limiting means and responsive to said digital amplitude signal, delay means responsive to said threshold comparator means, accumulator means responsive to said threshold comparator means, subtractor means responsive to said delay means and to said accumulator means, and coupled to an input of said accumulator means, dividing means coupled to the output of said accumulator means to provide a threshold error signal, and detector comparator means coupled to said dividing means for receiving said threshold error signal and responsive to said digital amplitude signal for detecting the occurrences of the value of said digital signal exceeding a controlled threshold value with a substantially constant false alarm rate.
Claim 3
Dependent Claim
29 words
The detector of claim 1 in which said accumulator means includes an adder for combining the output of said subtractor means and the output of said threshold comparator means.
Claim 4
Dependent Claim
32 words
The combination of claim 2 in which said threshold comparator means includes n threshold circuits each having a threshold at a different signal level with each providing a single bit output signal.
Claim 5
Dependent Claim
45 words
The detector of claim 3 in which said dividing means includes subtractor means for subtracting an expected value from the output of said subtractor means and includes a divider circuit responsive to said subtractor means for applying said threshold error signal to said detector comparator.
Claim 6
Dependent Claim
34 words
The detector of claim 4 in which said detector comparator means includes means for selecting detector thresholds and means for combining the selected threshold with said threshold error signal provided by said divider means.
Claim 7
Dependent Claim
311 words
A mean level detecting system for providing a substantially constant false alarm rate and being responsive to a digital radar signal having a selected plurality of bits during each of a plurality of clock intervals comprising amplitude limiting means responsive to said digital radar signal to pass a selected number of the least significant bits of said digital amplitude signal, threshold comparator means coupled to said amplitude limiting means and responsive to the least significant bits of said digital amplitude signal and having a plurality of threshold values for providing a threshold code signal representative of the value of said digital radar signal, delay means responsive to said threshold comparator means and providing a delay equal to a selected number of said clock intervals, accumulator means for accumulating a sum of the value of the signal provided by the threshold comparator means for a predetermined number of clock intervals, first subtractor means coupled to said delay means and to said accumulator means for subtracting the oldest data from said accumulated sum, first adder means coupled to said accumulator means and coupled to said threshold comparator means and to said subtractor means for combining the newest data with the output of said first subtractor means, second subtractor means coupled to said accumulator means and including means for storing an expected accumulated sum for subtracting the accumulated sum therefrom to provide a difference signal, dividing means coupled to said second subtractor means for scaling said difference signal, second adder means coupled to said dividing means, threshold code selection means coupled to said second adder means, signal delay means responsive to said digital radar signal, and detector means coupled to said second adder means and to said signal delay means for comparing the delayed digital signal with said threshold code after said code is combined with the scaled signal provided by said dividing means.
Claim 8
Dependent Claim
311 words
A mean level detecting system for providing a substantially constant false alarm rate and being responsive to a digital radar signal having a selected plurality of bits during each of a plurality of clock intervals comprising amplitude limiting means responsive to said digital radar signal to pass a selected number of the least significant bits of said digital amplitude signal, threshold comparator means coupled to said amplitude limiting means and responsive to the least significant bits of said digital amplitude signal and having a plurality of threshold values for providing a threshold code signal representative of the value of said digital radar signal, delay means responsive to said threshold comparator means and providing a delay equal to a selected number of said clock intervals, accumulator means for accumulating a sum of the value of the signal provided by the threshold comparator means for a predetermined number of clock intervals, first subtractor means coupled to said delay means and to said accumulator means for subtracting the oldest data from said accumulated sum, first adder means coupled to said accumulator means and coupled to said threshold comparator means and to said subtractor means for combining the newest data with the output of said first subtractor means, second subtractor means coupled to said accumulator means and including means for storing an expected accumulated sum for subtracting the accumulated sum therefrom to provide a difference signal, dividing means coupled to said second subtractor means for scaling said difference signal, second adder means coupled to said dividing means, threshold code selection means coupled to said second adder means, signal delay means responsive to said digital radar signal, and detector means coupled to said second adder means and to said signal delay means for comparing the delayed digital signal with said threshold code after said code is combined with the scaled signal provided by said dividing means.
Claim 9
Dependent Claim
20 words
The combination of claim 6 in which said amplitude limiting means passes two least significant bits to provide hard limiting.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |