US3701149A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency averaging controlled false alarm rate (cfar) circuit
Assignee: United States Department of the Navy
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Filing: 1971-07-02
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Granted: 1972-10-24
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Expires: 1991-07-02
Abstract
Abstract A frequency averaging CFAR circuit having a digital filter bank for receiving radar doppler echoes that are conducted sequentially into serially connected metal oxide semiconductor (MOS) type delay shift register networks with the outputs of shift registers on opposite sides of a center frequency register being summed to produce an average value applied to a threshold circuit together with the output of the center frequency register output to cause the threshold level to vary in accordance with the averaged noise and clutter signals and to detect a target signal whenever the output of the center frequency register exceeds the threshold.
Inventors
- 👤 Terence R Patton
- 👤 Melvin B Ringel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:46
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/50; G01S13/52; G01S13/522; G01S13/524; G01S13/5246
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
174 words
A frequency averaging CFAR circuit comprising: a digital filter bank for receiving pulse doppler radar echo signals therein and storing same; a plurality of serially coupled shift register stages having an input to the series and an output from each register, a central register being representative of the center frequency; a threshold detector having a threshold level input, a signal input coupled to said output of said central register, and an output; a summing circuit having a plurality of inputs coupling the outputs of said serially coupled registers other than said center register and having an output coupled to said threshold level input; and a means to produce sequential readout of said digital filter bank into said plurality of serially coupled registers and to shift said inputs to said plurality of serially coupled registers in serial sequence therethrough whereby said summing circuit averages all signals sequentially proceeding through said registers to vary the threshold voltage proportional to noise and clutter signals along with a plurality of echo signals to control the false alarm rate.
Claim 2
Dependent Claim
174 words
A frequency averaging CFAR circuit comprising: a digital filter bank for receiving pulse doppler radar echo signals therein and storing same; a plurality of serially coupled shift register stages having an input to the series and an output from each register, a central register being representative of the center frequency; a threshold detector having a threshold level input, a signal input coupled to said output of said central register, and an output; a summing circuit having a plurality of inputs coupling the outputs of said serially coupled registers other than said center register and having an output coupled to said threshold level input; and a means to produce sequential readout of said digital filter bank into said plurality of serially coupled registers and to shift said inputs to said plurality of serially coupled registers in serial sequence therethrough whereby said summing circuit averages all signals sequentially proceeding through said registers to vary the threshold voltage proportional to noise and clutter signals along with a plurality of echo signals to control the false alarm rate.
Claim 3
Dependent Claim
26 words
A frequency having CFAR circuit as set forth in claim 1 wherein said plurality of digital registers are metal oxide semiconductor type delay shift register stages.
Claim 4
Dependent Claim
62 words
A frequency averaging CFAR circuit as set forth in claim 2 wherein said summing circuit includes a first and second summing network for each set of registers preceding and succeeding said central register, and a third summing network coupling the outputs of said first and second summing networks for each set of registers to produce said output to said threshold level input.
Claim 5
Dependent Claim
37 words
A frequency averaging CFAR circuit as set forth in claim 3 wherein said means to produce sequential readout of said digital filter bank and to shift signals through said shift register in sequence is a clock circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |