US4061928A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for the protection of inputs of integrated MOS circuits
Assignee: Siemens AG
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Filing: 1976-08-25
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Granted: 1977-12-06
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Expires: 1996-08-25
Abstract
Abstract A circuit arrangement for the protection of inputs of integrated MOS circuits against excessive voltages, for example as a consequence of static charges, includes a first circuit means connected to the MOS circuit and having two bypass circuits reacting at different input voltage values and having a high-ohmic compensating resistance, and second circuit means is connected ahead of the first circuit and comprises a bypass circuit and a high-ohmic compensating resistance.
Inventors
- 👤 Heinrich Hubert Kessler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:43
CPC Classifications
H; H02; H02H; H02H9/00; H02H9/04; H02H9/045; H02H9/046; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
157 words
A protection circuit for protecting an input of an integrated MOS circuit against excessive voltages, the integrated MOS circuit connected across first and second supply terminals, comprising: an input; a pn bypass diode connected between said input and the first supply terminal; a first MOS transistor including a source-drain path connected between the second supply terminal and an input of said MOS circuit and a gate connected to said input of said MOS circuit; a gate controlled pn diode connected between said input of said MOS circuit and the first supply terminal; a first resistor connected with a first terminal to said input of said MOS circuit; a second MOS transistor including a source-drain path connected between a second terminal of said first resistor and said first supply terminal and a gate connected to said second terminal of said first resistor; and a second resistor connected between said second terminal of said first resistor and said input.
Claim 2
Dependent Claim
157 words
A protection circuit for protecting an input of an integrated MOS circuit against excessive voltages, the integrated MOS circuit connected across first and second supply terminals, comprising: an input; a pn bypass diode connected between said input and the first supply terminal; a first MOS transistor including a source-drain path connected between the second supply terminal and an input of said MOS circuit and a gate connected to said input of said MOS circuit; a gate controlled pn diode connected between said input of said MOS circuit and the first supply terminal; a first resistor connected with a first terminal to said input of said MOS circuit; a second MOS transistor including a source-drain path connected between a second terminal of said first resistor and said first supply terminal and a gate connected to said second terminal of said first resistor; and a second resistor connected between said second terminal of said first resistor and said input.
Claim 3
Dependent Claim
16 words
The protection circuit of claim 1, wherein said second MOS transistor comprises a thick-oxide MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-05 | 1981-06-06 | 1981-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-05 | 1985-06-06 | 1985-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-05 | 1989-06-06 | 1989-12-06 | $7700.00 | Window Closed / Lapsed |