Method and apparatus for driving electrochromic display device

Claim 2

In an electronic timepiece having a frequency standard for providing a higher frequency signal, a frequency converter to divide the higher frequency signal down to a lower frequency signal, a time counter coupled to the frequency converter to provide time information signals in response to the lower frequency signal, a decoder coupled to the time counter for generating decoded signals in dependence on the time information signals, and an electrochromic display device having display elements for displaying the decoded signals, the combination comprising: signal generation means coupled between the frequency converter and the time counter to generate frst, second and third phase signals in response to the lower frequency signal; means for presetting the count value in the time counter to cuase said time counter to provide a count value signal prior to a time represented by said count value signal; a first latch circuit coupled to the decoder and responsive to said second phase signal and said decoded signals to generate a bleaching signal for bleaching the display elements at a first timing; a second latch circuit coupled to the decoder and responsive to said third phase signal and said decoded signals to generate a coloration signal for coloring the display elements at a second timing.

Claim 3

The combination according to claim 1, in which said signal generation means comprises a decade decimal counter.

Claim 4

The combination according to claim 1, further comprising a driver circuit coupled to said first and second latch circuits for driving the display elements of the electrochromic display device in response to the bleaching signal and the coloration signal.

Claim 5

The combination according to claim 3, in which said driver circuit comprises first and second switching means coupled to said first and second latch circuits.

Claim 6

The combination according to claim 4, in which said first switching means comprises a first metal oxide semiconductor field-effect transistor having its gate terminal coupled through an inverter to said first latch circuit and its source terminal coupled to a positive potential, and a second metal oxide semi-conductor field-effect transistor having its gate terminal coupled to said second latch circuit and its source terminal coupled to a negative potential, said first and second metal oxide semiconductor field-effect transistors having drain terminals coupled together and connected to one side of each display element, and in which said second switching means comprises a first metal oxide semiconductor field-effect transistor having its gate terminal coupled through an inverter to said second latch circuit and its source terminal coupled to the positive potential, and a second metal oxide semiconductor field-effect transistor having its gate terminal coupled to said first latch circuit and its source terminal coupled to the negative potential, said first and second metal oxide semiconductor field-effect transistors of said second switching means having drain terminals coupled together and connected to another side of said each display element, said first metal oxide semiconductor field-effect transistor of said first switching means and said second metal oxide semiconductor field-effect transistor of said second switching means being conductive in response to said bleaching signal to cause an electric current to flow through said each display element in a bleaching direction while said first metal oxide semiconductor field-effect transistor of said second switching means and said second metal oxide semiconductor field-effect transistor of said first switching means being conductive in response to said coloration signal to cause the electric current to flow through said each display element in a coloring direction.

Claim 7

The combination according to claim 1, in which each of said first and second latch circuits comprises a first and second flip-flop, together with an AND gate, a normally high-level output terminal of said first flip-flop being connected to a data terminal of said second flip-flop and also to a first input terminal of said AND gate, and with a normally low-level output terminal of said second flip-flop connected to a second intput terminal of said AND gate, with said second phase signal being connected to a clock input terminal of said first flip-flop of said first latch circuit and with said third phase signal being connected to a clock input terminal of said second flip-flop of said first latch circuit.

Claim 8

The combination according to claim 6 in which said third phase signal and said second phase signal are applied to a clock terminal of said first flip-flop and of said second flip-flop of said second latch circuit, respectively.

Claim 9

The combination according to claim 6, further comprising an inverter, with an output of said inverter being connected to a data input of said first flip-flop of said first latch circuit and one of said decoded signals being applied to an input of said inverter and also applied to a data input of said first flip-flop of said second latch circuit.

Claim 10

The combination according to claim 6, in which said second and third phase signals are applied to an input of said AND gate of said first latch circuit and to an input of said AND gate of said second latch circuit, respectively.