Sensing amplifier for capacitive MISFET memory

Claim 2

A sensing amplifier for sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising: an input terminal for receiving the output signal from said memory cell; an output terminal; first and second sensing MISFETs, the sources of said first and second sensing MISFETs being connected to a first reference potential, the drain of said first sensing MISFET being connected to the gate of said second sensing MISFET and to said output terminal, the drain of said second sensing MISFET being connected to said input terminal; and a signal level shifting circuit connected to said input terminal at an input side thereof and to the gate of said first sensing MISFET at an output side thereof for shifting the level of the output signal from said memory cell, the level-shifted output signal being applied to the gate of said first sensing MISFET.

Claim 3

A sensing amplifier as set forth in claim 1, further comprising a preconditioning circuit including capacitive means having its one end connected to said first reference potential and the other end connected to said input terminal, precharge means connected between a second reference potential and said input terminal for precharging said capacitive means in response to a first clock signal prior to the application of the output signal from said memory cell to said sensing amplifier to preset said sensing amplifier, and means connected between said second reference potential and the drain of said first sensing MISFET for coupling said second reference potential to the drain of said first sensing MISFET in response to a second clock signal after the presetting of said sensing amplifier.

Claim 4

A sensing amplifier as set forth in claim 2, wherein said signal level shifting circuit comprises a series circuit connected between said first and second reference potentials, said series circuit including a drive MISFET whose gate is connected to said input terminal and load means having a first load MISFET whose gate is connected to the drain of said first sensing MISFET, a junction point of said series circuit being connected to the gate of said first sensing MISFET.

Claim 5

A sensing amplifier as set forth in claim 3, wherein said load means further includes a second load MISFET whose source and drain are connected to the source of and the drain of said first load MISFET respectively and whose gate is coupled to said second clock signal, the level of said level-shifted output signal from said signal level shifting circuit being determined by the ratio of said drive MISFET to said second load MISFET.

Claim 6

A sensing amplifier as set forth in claim 3, wherein said load means further includes a resistor connected between the source and drain of said first load MISFET.

Claim 7

A sensing amplifier as set forth in claim 2, wherein said signal level shifting circuit includes a series circuit which has a first capacitor connected to said input terminal and a second capacitor connected to said first reference potential and second precharge means connected between said second reference potential and a junction point of said first and second capacitors for precharging said second capacitor in response to said first clock signal, said junction point of said first and second capacitors being connected to the gate of said first sensing MISFET.

Claim 8

A sensing amplifier sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising: an input terminal for receiving the output signal from said memory cell; an output terminal; first and second sensing MISFETs, the sources of said frist and second sensing MISFETs being connected to a first reference potential, the drain of said first sensing MISFET being connected to the gate of said second sensing MISFET and to said output terminal, the drain of said second sensing MISFET being connected to said input terminal; capacitive means having its one end connected to said first reference potential and the other end connected to said input terminal; precharge means, connected between a second reference potential and said input terminal, for precharging said capacitive means in response to a first clock signal prior to the application of the output signal from said memory cell to said sensing amplifier to preset said sensing amplifier; means, connected between said second reference potential and the drain of said first sensing MISFET, for coupling said second reference potential to the drain of said first sensing MISFET in response to a second clock signal after the presetting of said sensing amplifier; and a signal level shifting circuit for shifting the level of out output signal from said memory to apply the level-shifted output signal to the gate of said first sensing MISFET, said signal level shifting circuit including a drive MISFET whose gate is connected to said input terminal and a first load MISFET whose gate is connected to the drain of said first sensing MISFET, the drain of said drive MISFET being connected to said second reference potential, the source of said drive MISFET and the drain of said first load MISFET being connected to each other and to the gate of said first sensing MISFET, the gate of said first load MISFET being connected to the drain of said first sensing MISFET and the gate of said second sensing MISFET, the source of said first load MISFET being connected to said first reference potential.

Claim 9

A sensing amplifier sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising: an input terminal for receiving the output signal from said memory cell; an output terminal; first and second sensing MISFETs, the sources of said frist and second sensing MISFETs being connected to a first reference potential, the drain of said first sensing MISFET being connected to the gate of said second sensing MISFET and to said output terminal, the drain of said second sensing MISFET being connected to said input terminal; capacitive means having its one end connected to said first reference potential and the other end connected to said input terminal; precharge means, connected between a second reference potential and said input terminal, for precharging said capacitive means in response to a first clock signal prior to the application of the output signal from said memory cell to said sensing amplifier to preset said sensing amplifier; means, connected between said second reference potential and the drain of said first sensing MISFET, for coupling said second reference potential to the drain of said first sensing MISFET in response to a second clock signal after the presetting of said sensing amplifier; and a signal level shifting circuit for shifting the level of out output signal from said memory to apply the level-shifted output signal to the gate of said first sensing MISFET, said signal level shifting circuit including a drive MISFET whose gate is connected to said input terminal and a first load MISFET whose gate is connected to the drain of said first sensing MISFET, the drain of said drive MISFET being connected to said second reference potential, the source of said drive MISFET and the drain of said first load MISFET being connected to each other and to the gate of said first sensing MISFET, the gate of said first load MISFET being connected to the drain of said first sensing MISFET and the gate of said second sensing MISFET, the source of said first load MISFET being connected to said first reference potential.

Claim 10

A sensing amplifier as set forth in claim 7, wherein said signal level shifting circuit further includes a second load MISFET whose source and drain are connected to the source and drain of said first load MISFET respectively and whose gate is coupled to a second clock signal.

Claim 11

A sensing amplifier as set forth in claim 7, wherein said signal level shifting circuit further includes a resistor connected between the source and drain of said first load MISFET.

Claim 12

A sensing amplifier for sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising: an input terminal for receiving the output signal from said memory cell; an output terminal; a latch circut including a first and second MISFETs whose junction point is connected to said input terminal and a second inverter having third and fourth MISFETs whose junction point is connected to said output terminal, first and second clock signals being applied to the gates of said first and third MISFETs respectively, the gate of said second MISFET being connected to said output terminal; and a signal level shifting circuit connected to said input terminal at an input side thereof and to the gate of said fourth MISFET at an output side thereof for shifting the level of the output signal of said memory cell to apply the level-shifted output signal to the gate of said fourth MISFET.

Claim 13

A sensing amplifier for sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising: an input terminal for receiving the output signal from said memory cell; an output terminal; a latch circut including a first and second MISFETs whose junction point is connected to said input terminal and a second inverter having third and fourth MISFETs whose junction point is connected to said output terminal, first and second clock signals being applied to the gates of said first and third MISFETs respectively, the gate of said second MISFET being connected to said output terminal; and a signal level shifting circuit connected to said input terminal at an input side thereof and to the gate of said fourth MISFET at an output side thereof for shifting the level of the output signal of said memory cell to apply the level-shifted output signal to the gate of said fourth MISFET.

Claim 14

A sensing amplifier as set forth in claim 10, wherein said signal level shifting circuit includes a drive MISFET whose gate is connected to said input terminal and load means having a first load MISFET whose gate is connected to the gate of said second MISFET of said latch circuit and to said output terminal, a junction point of said drive MISFET and said first load MISFET being connected to the gate of said fourth MISFET of said latch circuit.

Claim 15

A sensing amplifier as set forth in claim 11, wherein said load means further has a second load MISFET whose source and drain are connected to the source and drain of said first load MISFET respectively and whose gate is coupled to said second clock signal.

Claim 16

A sensing amplifier as set forth in claim 11, wherein said load means further has a resistor connected between the source and drain of said first load MISFET.

Claim 17

A sensing amplifier as set forth in claim 10, wherein said signal level shifting circuit includes precharge means and a series circuit of first and second capacitors, one end of said first capacitor being connected to said input terminal, a junction point of said first and second capacitors being connected to said precharge means and to the gate of said fourth MISFET of said latch circuit, said precharge means precharging said second capacitor in response to said first clock signal.