Patent US4056820A successfully refreshed from Google Patents.
US4056820A
Expired / Lapsed
US
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Reversible analog to digital converter
Assignee: Siemens AG
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Filing: 1976-07-27
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Granted: 1977-11-01
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Expires: 1996-07-27
Abstract
Abstract A switching arrangement for converting analog signals into digital signals, and vice versa, is described. Conversions between pulse amplitude modulated (PAM) and pulse code modulated (PCM) signals are performed. In telecommunication systems having subscriber stations equipped to transmit and receive analog signals it is necessary to carry out these conversions to facilitate PCM transmission. An analog to digital converter is thus provided at each subscriber station for converting received digital signals into analog signals and analog signals to be transmitted into digital signals; the converter utilizes the iterative principle.
Inventors
- 👤 Ernst Hofer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:17
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/02
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
248 words
Apparatus for converting analog signals from a source thereof into digital signals for transmission and transmitted digital signals into analog signals for an analog receiver, comprising: digital to analog converter means, comparator means having a first input connected to an output of said digital to analog converter means and a second input connected to receive said analog signals from said source, a multistage binary counter, intermediate register means having a plurality of bistable stages, first logic means coupled to receive an output from said comparator means and to enable communication of outputs from predetermined ones of said stages of said counter to respective ones of said stages of said intermediate register, means coupled to a first predetermined stage of said binary counter and responsive to an output signal therefrom for enabling the communication of a digital signal to be converted to said digital to analog converter during a first interval when a digital to analog conversion is to take place gate means coupled to a second predetermined stage of said binary counter and responsive to an output signal therefrom for rendering said digital to analog converter operative during an interval when an analog to digital conversion is to take place, output register means having inputs connected, respectively, to outputs of said intermediate register for producing output digital signals, and input register means having an input for receiving digital signals to be converted and outputs connected, respectively, to set inputs of said bistable stages of said intermediate register means.
Claim 2
Dependent Claim
248 words
Apparatus for converting analog signals from a source thereof into digital signals for transmission and transmitted digital signals into analog signals for an analog receiver, comprising: digital to analog converter means, comparator means having a first input connected to an output of said digital to analog converter means and a second input connected to receive said analog signals from said source, a multistage binary counter, intermediate register means having a plurality of bistable stages, first logic means coupled to receive an output from said comparator means and to enable communication of outputs from predetermined ones of said stages of said counter to respective ones of said stages of said intermediate register, means coupled to a first predetermined stage of said binary counter and responsive to an output signal therefrom for enabling the communication of a digital signal to be converted to said digital to analog converter during a first interval when a digital to analog conversion is to take place gate means coupled to a second predetermined stage of said binary counter and responsive to an output signal therefrom for rendering said digital to analog converter operative during an interval when an analog to digital conversion is to take place, output register means having inputs connected, respectively, to outputs of said intermediate register for producing output digital signals, and input register means having an input for receiving digital signals to be converted and outputs connected, respectively, to set inputs of said bistable stages of said intermediate register means.
Claim 3
Dependent Claim
28 words
The apparatus defined in claim 1 wherein said bistable stages of said intermediate register means have reset inputs connected to a third predetermined output of said binary counter.
Claim 4
Dependent Claim
25 words
The apparatus defined in claim 2 wherein said reset inputs to said bistable stages are connected additionally to a sixth output from said binary counter.
Claim 5
Dependent Claim
42 words
The apparatus defined in claim 1 wherein the outputs of said input register are connected to the set inputs of said intermediate register by means of second logic means having enabling inputs connected to a fourth predetermined output of said binary counter.
Claim 6
Dependent Claim
36 words
The apparatus defined in claim 1 further comprising switch means operative responsive to a fifth predetermined output from said binary counter for connecting an analog output from said digital to analog converter to said analog receiver.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |