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US3900844A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog and digital data interconversion system

Assignee: Honeywell Inc
•
Filing: 1973-10-03
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Granted: 1975-08-19
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Expires: 1993-10-03
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Abstract

Abstract A system for interconverting analog and digital signals in a large number of data channels using supervisory apparatus common to all the channels.

Inventors

  • 👤 Leon D Wald

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 18:43
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; Y; Y10; Y10S; Y10S177/00; Y10S177/03

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 253 words
Apparatus for interconverting analog and digital signals comprising, in combination: a source of clock pulses; a cycle strobe pulse source for giving a strobe pulse output after each predetermined number of clock pulses; an n-bit, 2''s complement counter giving a first count output which cyclicly passes through a range of values extending from a maximum to a minimum; a (n-1)-bit, magnitude-only counter giving a second count output which cyclicly passes through a range of values extending from a maximum to a minimum; means connecting said counters for simultaneous actuation by said clock pulses; means for presetting said counters to maximum values in response to said strobe pulse output; a bipolar digital-to-analog converter giving an analog output determined in magnitude by the second count output and in sign by a sign bit from said n-bit counter; and a converter channel including first and second converting means each receiving the first count and analog outputs, said first converting means for receiving an input digital signal and including means comparing the input digital signal with the first count output and giving an output signal determined by the value of the analog output at the time the first count output becomes equal to the input digital signal, said second converting means for receiving an input analog signal and including means comparing the input analog signal with the analog output and giving a digital output signal determined by the value of the first digital output at the time the analog output becomes less than the input analog signal.
Claim 2
Dependent Claim 253 words
Apparatus for interconverting analog and digital signals comprising, in combination: a source of clock pulses; a cycle strobe pulse source for giving a strobe pulse output after each predetermined number of clock pulses; an n-bit, 2''s complement counter giving a first count output which cyclicly passes through a range of values extending from a maximum to a minimum; a (n-1)-bit, magnitude-only counter giving a second count output which cyclicly passes through a range of values extending from a maximum to a minimum; means connecting said counters for simultaneous actuation by said clock pulses; means for presetting said counters to maximum values in response to said strobe pulse output; a bipolar digital-to-analog converter giving an analog output determined in magnitude by the second count output and in sign by a sign bit from said n-bit counter; and a converter channel including first and second converting means each receiving the first count and analog outputs, said first converting means for receiving an input digital signal and including means comparing the input digital signal with the first count output and giving an output signal determined by the value of the analog output at the time the first count output becomes equal to the input digital signal, said second converting means for receiving an input analog signal and including means comparing the input analog signal with the analog output and giving a digital output signal determined by the value of the first digital output at the time the analog output becomes less than the input analog signal.
Claim 3
Dependent Claim 134 words
Apparatus according to claim 1 including: a plurality of converter channels having first and second converting means each receiving the first count and analog outputs and an input digital signal, including means comparing the input digital signal with the first count signal and giving an analog output signal determined by the value of the analog output at the time the first count signal becomes equal to the input digital signal; and a plurality of converter channels having first and second converting means each receiving the first count and analog outputs and an input analog signal, including means comparing the input analog signal with the analog output and giving a digital output signal determined by the value of the first count output at the time the analog output becomes less than the input analog signal.
Claim 4
Dependent Claim 108 words
Apparatus according to claim 1 in which said first converting means includes: a buffer register arranged to be set in accordance with the input digital signal; a digital comparator connected to receive the first count output and the output of said register, and to give a further output when the inputs thereto become equal; and an analog gate connected to receive the further output and the analog output, for giving an analog output signal determined by the value of the latter at the time when said inputs to said digital comparator become equal, which does not thereafter change as the analog output contiNues through its cycle of values.
Claim 5
Dependent Claim 23 words
Apparatus according to claim 3 in which said buffer register is loaded with said input digital signal concurrently with resetting of said counters.
Claim 6
Dependent Claim 69 words
Apparatus according to claim 1 in which said second converting means includes: a sample-and-hold circuit; an analog comparator comparing the output of said sample-and-hold circuit with the analog output and operating to give a control output when the latter becomes smaller than the former; a buffer register; and means setting said reegister in accordance with the value of the first count output at the time said analog comparator operates.
Claim 7
Dependent Claim 46 words
Apparatus according to claim 5 in which said clock pulse source also supplies delayed pulses, and in which said second converting means further includes logic means actuated by said delayed pulses for preventing said register from being set except at the time said analog comparator operates.

References Cited (Backward Citations)

US2865564A Cited
US2817704A Cited
US2950348A Cited
US3403393A Cited
US3541544A Cited
US3540037A Cited
US3824588A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-08-18 1979-02-17 1979-08-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-08-18 1983-02-17 1983-08-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-08-18 1987-02-17 1987-08-19 $7700.00 Window Closed / Lapsed

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