Electronically alterable diode logic circuit

Claim 2

A logic circuit which comprises a. a row column array, MxN in number, of three-terminal electrically unidirectional and reprogrammable logic cells, each cell having a first and a second high current carrying terminal and a third low current carrying gate terminal, b. a plurality of M first electrically conductive row line means for connecting together the third terminals of all cells in each row to a different gate write-in row terminal, c. a plurality of M second electrically conductive row line means for connecting together the first terminals of all cells in each row to a different row line signal terminal, d. a plurality of N third electrically conductive column line means for connecting together the second terminals of all cells in each column to a different one of said column lines, each column line connected at one terminal thereof to a different two-terminal column electrical load element for inhibiting current in the opposite sense of direction from said unidirectional cell and each column line having a column signal terminal.

Claim 3

The circuit of claim 1 further comprising fourth electrically conductive line means for connecting together a second load terminal of each of the said load elements to a single array write-enable terminal, said load elements each characterized by current inhibition in one sense of direction and by an impedence load for supporting a predetermined write-enable voltage drop in the other sense of direction.

Claim 4

The circuit of claim 2 which further comprises a plurality of M write-in gate row switching means each connected to a different one of the gate write-in row terminals, in order to provide voltages to each said row sufficient to program the memory logic state of at least one cell in said row into a first logic state and into a second, different logic state.

Claim 5

The circuit of claim 3 which further includes a plurality of N column switching means each connected to a different one of the column line signal terminals, in order to select each column line for connection to a different voltage detector.

Claim 6

The circuit of claim 4 in which each of said voltage detectors connected to a given column line through one of said column switching means has an electrical resistance with respect to current flowing in the said one direction that is less than that of the corresponding one of said load elements connected to said one terminal of said column line with respect to said current.

Claim 7

The circuit of claim 4 which further comprises a plurality of M row resistance elements, each of said row resistance elements having a first row resistance terminal connected to a different one of the row line signal terminals and a second row resistance terminal mutually connected to every other of the second row resistance terminals, each of said row resistance elements characterized by an electrical resistance that is less than that of the resistance of every voltage detector.

Claim 8

The circuit of claim 3 which further comprises row switching means connected to said signal row terminals and column switching means connected to said signal column terminals, for selecting a single logic cell for addressing by an external voltage.

Claim 9

The circuit of claim 1 which further comprises a plurality of M write-in gate row switching means each connected to a different one of the gate write-in row terminals, in order to provide voltage to each said row sufficient to program the memory logic state of at least one cell in said row.

Claim 10

The circuit of claim 1 which further includes a plurality of N column switching means each connected to a different one of the column line signal terminals, in order to select each column line for connection to a voltage detector.

Claim 11

The circuit of claim 1 in which each logic cell consists essentially of a different memory transistor element containing the said low current gate terminal and having a high current path connected in series with a separate unidirectional current inhibitor element.

Claim 12

The circuit of claim 10 further comprising fourth electrically conductive line means for connecting together a second load terminal of all the said load elements to a single array write-enable terminal, said load elements each characterized by current inhibition in one sense of direction and by an impedance load for supporting a predetermined write-enable voltage in the other sense of direction.

Claim 13

The circuit of claim 11 which further comprises a plurality of M write-in gate row switching means each connected to a different one of the gate write-in row terminals, in order to provide voltage to each said row sufficient to program the memory logic state of at least one cell in said row.

Claim 14

The circuit of claim 12 which further includes a plurality of N column switching means each connected to a different one of the column line signal terminals, in order to select each column line for connection to a voltage detector.

Claim 15

The circuit of claim 13 in which each of said voltage detectors connected to a given column line through one of said column switching means has an electrical resistance with respect to current flowing in the said one direction that is less than that of the corresponding one of said load elements connected at the opposite end of said column line with respect to said direction.

Claim 16

The circuit of claim 14 which further comprises a plurality of M row resistance elements, each of said row resistance elements having a first row resistance terminal connected to a different one of the row line signal terminals and a second row resistance terminal mutually connected to every other of the second row resistance terminals, each of said unidirectional row resistance elements characterized by current inhibition in only one sense of direction.

Claim 17

The circuit of claim 15 in which each of said voltage detectors has an electrical resistance that is greater than every one of the said row resistance elements.

Claim 18

The circuit of claim 16 which further comprises row switching means connected to said signal row terminals and column switching means connected to said signal column terminals, for selecting a single logic cell connected at the crosspoint of each row and column for application thereto of an external voltage.

Claim 19

The circuit of claim 17 which further comprises a plurality of M write-in gate row switching means each connected to a different one of the gate write-in row terminals, in order to provide voltage to each said row sufficient to program the memory logic state of at least one cell in said row.

Claim 20

The circuit of claim 18 which further includes a plurality of N column switching means each connected to a different one of the column line signal terminals, in order to select each column line for connection to a voltage detector.

Claim 21

Semiconductor apparatus which comprises a. a row-column MxN array of three-terminal logic cells, each cell having a different first high current cell terminal and a different second high current cell terminal thereby defining a separate high current path for each cell, each cell consisting essentially of a different electrically programmable semiconductor memory element in series with a separate unidirectional inhibitor element for passing high current through the logic cell between the first and second high current cell terminals only in one sense of direction and inhibiting current in the other sense of direction, each said memory element having a low current cell gate terminal for the application of voltage to program the memory element, b. a first plurality, M in number, of electrically conductive row gate line means, each for mutually connecting together the said low current gate terminals of the memory elements in all cells of each row to a different gate write-in row terminal, c. a second plurality, M in number, of electrically conductive row line means, each for mutually connecting together the first high current terminals of all cells in each row to a different row line signal terminal, d. a third plurality, N in number, of electrically conductive column line means for mutually connecting together the second high current terminals of all cells in each row to a different column line signal terminal and to a column load terminal, and e. means for connecting each column load terminal to a first terminal of a different two-terminal column load element for inhibiting current in said one sense of direction.

Claim 22

Semiconductor apparatus which comprises a. a row-column MxN array of three-terminal logic cells, each cell having a different first high current cell terminal and a different second high current cell terminal thereby defining a separate high current path for each cell, each cell consisting essentially of a different electrically programmable semiconductor memory element in series with a separate unidirectional inhibitor element for passing high current through the logic cell between the first and second high current cell terminals only in one sense of direction and inhibiting current in the other sense of direction, each said memory element having a low current cell gate terminal for the application of voltage to program the memory element, b. a first plurality, M in number, of electrically conductive row gate line means, each for mutually connecting together the said low current gate terminals of the memory elements in all cells of each row to a different gate write-in row terminal, c. a second plurality, M in number, of electrically conductive row line means, each for mutually connecting together the first high current terminals of all cells in each row to a different row line signal terminal, d. a third plurality, N in number, of electrically conductive column line means for mutually connecting together the second high current terminals of all cells in each row to a different column line signal terminal and to a column load terminal, and e. means for connecting each column load terminal to a first terminal of a different two-terminal column load element for inhibiting current in said one sense of direction.

Claim 23

Semiconductor apparatus according to claim 20 in which each memory element is electrically reprogrammable.

Claim 24

Semiconductor apparatus according to claim 21 in which each said column load element has a second terminal connected to a common write-enable terminal.

Claim 25

Semiconductor apparatus according to claim 22 which further comprises a plurality of M write-in gate row switching means each connected to a different one of the gate write-in row terminals, in order to provide voltage to each said row sufficient to program the memory logic state of at least one cell in said row.

Claim 26

Semiconductor apparatus according to claim 23 which further includes a plurality of N column switching means each connected to a different one of the column line signal terminals, in order to select each column line for connection to a voltage detector.

Claim 27

Semiconductor apparatus according to claim 24 in which each of said voltage detectors connected to a given column line through one of said column switching means has an electrical resistance with respect to current flowing in a predetermined direction that is less than that of the corresponding one of said column load elements.

Claim 28

Semiconductor apparatus according to claim 21 which further comprises a plurality of M write-in gate row switching means each connected to a different one of the gate write-in row terminals, in order to provide voltages to each said row sufficient to program the memory logic state of at least one cell at a time in said row into a first logic state and into a second, different logic state.

Claim 29

Semiconductor apparatus according to claim 26 which further includes a plurality of N column switching means each connected to a different one of the column line signal terminals, in order to select each column line for connection to a voltage detector.