Phase locked loop for synchronizing VCO with digital data pulses

Claim 2

A phase-locked-loop phase detector for synchronizing pulse outputs of a voltage controlled oscillator with a train of data pulses spaced apart in integral multiples of a fundamental clock period comprising bistable means for providing an output voltage signal at an output terminal and having two input terminals, a first input terminal for triggering said bistable means into one state with said output voltage signal at a first predetermined level, and a second input terminal for holding said bistable means in another state with said output voltage signal at a second predetermined voltage level in response to a signal of a predetermined one of said high and low voltage signal levels, means for coupling the output pulses of said voltage controlled oscillator to said first terminal of said bistable means, thereby triggering said bistable means into said one state in response to an output pulse of said voltage controlled oscillator, means for coupling said train of data pulses to said second input terminal of said bistable means, with a predetermined pulse polarity for holding said bistable means in said other state during intervals between data pulses, coincidence gating means having two input terminals and one output terminal, one input terminal connected to receive said train of data pulses with said predetermined pulse polarity and the other input terminal connected to receive said output voltage signal of said bistable means, a source of reference voltage, and error signal generating means responsive to the output terminal of said gating means and said reference voltage for producing a phase error signal proportional to the pulse width of pulses at the output terminal of said gating means for control of said voltage controlled oscillator.

Claim 3

The combination of claim 1 wherein said bistable means has a second output terminal for producing a complementary output voltage signal, said combination including a second coincidence gating means having two input terminals and one output terminal, one input terminal connected to receive said train of data pulses with said predetermined pulse polarity, and the other input terminal connected to receive said complementary output voltage signal of said bistable means, and wherein said error signal generating means is responsive to the output of both gating means and said reference voltage for producing a phase error signal proportional to the difference in pulse width of pulses at the output terminals of both gating means.

Claim 4

In a phase-locked loop, a phase comparator capable of providing phase error magnitude and direction information for synchronizing a voltage controlled oscillator with a data pulse train which consists of pulses spaced apart in integral multiples of a fundamental clock period comprising oscillatory means controlled in period by a phase error signal for producing output pulses of the prime period of said data pulses in the absence of any phase error, of greater period in the presence of a phase error of a given polarity, and of lesser period in the presence of a phase error of opposite polarity, bistable means connected to receive said output pulses and train of data pulses at separate input terminals for producing complementary pulses at Q and Q output terminals thereof in response to being set at the end of each cycle of said oscillatory means while a data pulse is present and to being held clear whenever a data pulse is not present,

Claim 5

In a phase-locked loop, a phase comparator capable of providing phase error magnitude and direction information for synchronizing a voltage controlled oscillator with a data pulse train which consists of pulses spaced apart in integral multiples of a fundamental clock period comprising oscillatory means controlled in period by a phase error signal for producing output pulses of the prime period of said data pulses in the absence of any phase error, of greater period in the presence of a phase error of a given polarity, and of lesser period in the presence of a phase error of opposite polarity, bistable means connected to receive said output pulses and train of data pulses at separate input terminals for producing complementary pulses at Q and Q output terminals thereof in response to being set at the end of each cycle of said oscillatory means while a data pulse is present and to being held clear whenever a data pulse is not present,

Claim 6

first coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said Q output terminal of said bistable means for gating a pulse out while both input terminals thereof receive a binary signal of predetermined level, second coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said Q output terminal of said bistable means for gating a pulse out while both input terminals thereof receive a binary signal of said predetermined level, and means for producing said phase error signal directly proportional to the difference in the pulse widths of pulses gated out by said first and second coincidence gating means with a given polarity when pulses from said first gating means are greater, and of opposite polarity when pulses from said second gating means are greater.

Claim 7

first coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said Q output terminal of said bistable means for gating a pulse out while both input terminals thereof receive a binary signal of predetermined level, second coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said Q output terminal of said bistable means for gating a pulse out while both input terminals thereof receive a binary signal of said predetermined level, and means for producing said phase error signal directly proportional to the difference in the pulse widths of pulses gated out by said first and second coincidence gating means with a given polarity when pulses from said first gating means are greater, and of opposite polarity when pulses from said second gating means are greater.

Claim 8

A phase-locked loop employed to synchronize a voltage controlled oscillator with a data pulse train, where said data pulse train is comprised of pulses spaced apart in integral multiples of a fundamental clock period comprising a flip-flop having true and complementary output terminals, and having a first input terminal adapted to place said flip-flop in a first state with said true output terminal at a predetermined high voltage level and said complementary output terminal at a predetermined low voltage level in response to the end of a cycle of said oscillator in the presence of a data pulse, and having a second input terminal adapted to place said bistable means in a second state with said true output terminal at said low voltage level and said complementary output terminal at said high voltage level in response to the absence of a data pulse, first coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said true output terminal of said flip-flop for gating a pulse out while both input terminals receive a voltage signal at one of said predetermined levels, second coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said complementary output terminal of said bistable means for gating a pulse out while both input terminals receive a voltage signal at said one predetermined level, means for producing said phase error signal directly proportional to the difference in the pulse widths of pulses gated out by said first and second coincidence gating means with a given polarity when pulses from said first gating means are greater in width, and of opposite polarity when pulses from said second gating means are greater in width, and means for applying said phase error signal to said voltage controlled oscillator to control the frequency thereof.

Claim 9

A phase-locked loop employed to synchronize a voltage controlled oscillator with a data pulse train, where said data pulse train is comprised of pulses spaced apart in integral multiples of a fundamental clock period comprising a flip-flop having true and complementary output terminals, and having a first input terminal adapted to place said flip-flop in a first state with said true output terminal at a predetermined high voltage level and said complementary output terminal at a predetermined low voltage level in response to the end of a cycle of said oscillator in the presence of a data pulse, and having a second input terminal adapted to place said bistable means in a second state with said true output terminal at said low voltage level and said complementary output terminal at said high voltage level in response to the absence of a data pulse, first coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said true output terminal of said flip-flop for gating a pulse out while both input terminals receive a voltage signal at one of said predetermined levels, second coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said complementary output terminal of said bistable means for gating a pulse out while both input terminals receive a voltage signal at said one predetermined level, means for producing said phase error signal directly proportional to the difference in the pulse widths of pulses gated out by said first and second coincidence gating means with a given polarity when pulses from said first gating means are greater in width, and of opposite polarity when pulses from said second gating means are greater in width, and means for applying said phase error signal to said voltage controlled oscillator to control the frequency thereof.