Sense latch circuit for a bisectional memory array

Claim 2

A memory circuit comprising a plurality of memory cells arranged in an array of rows and columns, said memory cells each consisting of a single field effect transistor and a storage capacitor, said memory array being divided into first and second row groups; a plurality of cross-coupled differential amplifiers having first input terminals respectively connected to the memory cells belonging to said first row group and each column, and second input terminals respectively connected to the memory cells belonging to said second row group and each same column as that connected to said first terminal; and output sense amplifier having first and second input terminals; first means for operatively connecting the first terminal of a selected one of said differential amplifiers to said first terminal of said sense amplifier, and second means for operatively connecting the second terminal of said selected differential amplifier to said second terminal of said sense amplifier.

Claim 3

The memory circuit of claim 1, in which said first and second connecting means respectively include first and second switching means respectively operatively interposed between said memory cells belonging to said first and second groups in each column and said first and second terminals of said sense amplifier, and first and second addressing means for respectively activating a selected one of said first and second switching means.

Claim 4

The memory circuit of claim 2, in which said addressing means includes a first group of column decoders operatively connected to said first switching means, and a group of additional column decoders operatively connected to said second switching means.

Claim 5

The memory circuit of claim 1, in which said first connecting means includes first column selecting means for selecting said selected one of said differential amplifiers and said second connecting means includes additional column selecting means.

Claim 6

The memory circuit of claim 4, further comprising a plurality of first switch means respectively operatively connected between said first input terminals of said differential amplifiers and said first terminal of said sense amplifier, and a plurality of second switch means operatively connected between said second input terminals of said differential amplifiers and said second terminal of said sense amplifier, said first and second plurality of switch means being operatively selectively actuated by said first and said additional column selecting means.

Claim 7

A memory circuit comprising a plurality of memory cells arranged in an array of rows and columns, said array being divided into first and second row groups; a plurality of differential amplifiers having first input terminals respectively connected to the memory cells belonging to said first row group and each of said columns, and second input terminals respectively connected to the memory cells belonging to said second row group and each same column as that connected to said first input terminals; first and second input-output bus lines; first means for operatively connecting the first terminal of the selected differential amplifier to said first input-output bus line; second means for operatively connecting the second terminal of said selected differential amplifier to said second input-output bus line; and means for simultaneously supplying said first input-output bus line with one of the logic "1" and "0" signals and said second input-output bus line with the other of said logic "1" and "0" signals when said memory circuit is enabled in the write-operation mode.

Claim 8

A memory circuit comprising a plurality of memory cells arranged in an array of rows and columns, said array being divided into first and second row groups; a plurality of differential amplifiers having first input terminals respectively connected to the memory cells belonging to said first row group and each of said columns, and second input terminals respectively connected to the memory cells belonging to said second row group and each same column as that connected to said first input terminals; first and second input-output bus lines; first means for operatively connecting the first terminal of the selected differential amplifier to said first input-output bus line; second means for operatively connecting the second terminal of said selected differential amplifier to said second input-output bus line; and means for simultaneously supplying said first input-output bus line with one of the logic "1" and "0" signals and said second input-output bus line with the other of said logic "1" and "0" signals when said memory circuit is enabled in the write-operation mode.

Claim 9

The memory circuit of claim 6, further comprising an output sense amplifier having first and second input terminals, said first and second input terminals being connected to said first and second bus lines, respectively.

Claim 10

The memory circuit of claim 6, in which said supplying means includes first and second gates coupled to said first and second input-output bus lines, respectively, and means for transferring the true and complementary of input signals to said first and second bus lines, respectively, in response to a write command signal.