Drain source protected MNOS transistor and method of manufacture

Claim 1

A drain source protected MNOS transistor comprising a substrate of electrically insulating material, a mesa of N type semiconductor material deposited on the surface thereof, a source region formed by P+ diffusions into a portion of said mesa adjacent one edge thereof, a drain region formed by P+ diffusions into a portion of said mesa adjacent the edge thereof opposite said source region, a first region of gate silicon dioxide growth on said mesa surface covering a strip of the channel portion thereof opposite said source region, a second region of gate silicon dioxide growth on said mesa surface covering a strip of the channel portion thereof adjacent said drain region, a substrate gate window on said mesa surface in part defined by said first and second gate silicon dioxide growth regions, a tunneling silicon dioxide growth layer on and coextensive with said substrate gate window, a layer of memory silicon nitride on and coextensive with said tunneling silicon dioxide growth layer, a third region of gate silicon dioxide growth on said source region adjacent said first region of gate silicon dioxide, a fourth region of gate silicon dioxide on said drain region adjacent said second region of gate silicon dioxide, a first layer of silox on said third region of gate silicon dioxide, a second layer of silox on said fourth region of gate silicon dioxide, a drain electrode, a source electrode, and a gate electrode, said first and second regions of gate silicon dioxide growth being approximately 1000 A thick, said tunneling silicon dioxide growth layer being approximately 25 A thick, said third and fourth regions of gate silicon dioxide growth being approximately 300 A thick, said first and second layers of silox being approximately 10,000 A thick, and said memory silicon nitride layer being approximately 300 A thick.