Drive circuit for a display

Claim 2

In combination: at least one first multi-terminal semiconductor device, source means to supply a reference potential signal, power supply means connected to said source for boosting said reference potential signal, and driver means connected between said power supply means and said at least one semiconductor device and adapted to selectively apply said boosted signal to a control electrode of said first semiconductor device to thereby drive said device, said driver means including second and third multiterminal semiconductor devices, the conduction path of said second semiconductor device selectively connected between said power supply means and the control electrode of said at least one first semiconductor device, the conduction path of said third semiconductor device connected between one conduction path electrode and the control electrode of said second semiconductor device so as to form a feedback path therebetween, and the control electrode of said third device connected to the one conduction path electrode of said second device.

Claim 3

The combination recited in claim 1, including display means, said at least one first semiconductor device selectively connected between said source means and said display means in order to energize said display means.

Claim 4

The combination recited in claim 1, said driver means further including means to selectively connect said source means to the control electrode of said second semiconductor device, the control electrode of said second semiconductor device receiving a driving signal comprising said reference potential signal and a feedback signal via the one conduction path electrode of said second device and the conduction path of said third device, said driving signal sufficient to substantially reduce the impedance of said second device.

Claim 5

The combination recited in claim 3, wherein the means to selectively connect said source means to the control electrode of said second semiconductor device includes a voltage variable capacitor.

Claim 6

The combination recited in claim 4, wherein said capacitor is connected to clock terminal means, said clock terminal means adapted to receive a clock signal so as to supply the control electrode of said second device with said driving signal.

Claim 7

The combination recited in claim 1, including a fourth multiterminal semiconductor device connected in electrical parallel with said third semiconductor device, first conduction path electrodes of said third and fourth semi-conductor devices connected at a common electrical junction with said one conduction path electrode of said second semiconductor device and the control electrode of said first device.

Claim 8

In combination: at least one first multi-terminal semiconductor device, source means to provide a first reference potential signal, power supply means connected to said source means for boosting said first reference potential signal, and driver means connected between said power supply means and said at least one first semiconductor device to selectively apply said boosted signal to said first semiconductor device and thereby drive said device, said power supply means including second and third multi-terminal semiconductor devices, the respective conduction paths of each of said second and third semiconductor devices connected in electrical parallel with respect to one another between said source means and said driver means, the control electrode of said second device connected to one conduction path electrode thereof, and means to apply said boosted signal to the control electode of each of said second and third devices.

Claim 9

In combination: at least one first multi-terminal semiconductor device, source means to provide a first reference potential signal, power supply means connected to said source means for boosting said first reference potential signal, and driver means connected between said power supply means and said at least one first semiconductor device to selectively apply said boosted signal to said first semiconductor device and thereby drive said device, said power supply means including second and third multi-terminal semiconductor devices, the respective conduction paths of each of said second and third semiconductor devices connected in electrical parallel with respect to one another between said source means and said driver means, the control electrode of said second device connected to one conduction path electrode thereof, and means to apply said boosted signal to the control electode of each of said second and third devices.

Claim 10

The combination recited in claim 7, wherein the means to apply said boosted signal to each of the control electrodes of said second and third semiconductor devices includes first and second capacitors, respective first plates of said capacitors selectively connected to said source means to receive said first reference potential signal in order to charge said capacitors, and respective second plates of said capacitors connected together to selectively receive a second reference potential signal.

Claim 11

The combination recited in claim 8, including inverter means to selectively connect the respective first plates of said first and second capacitors to said source means to receive said first reference potential signal.

Claim 12

The combination recited in claim 8, including bootstrap inverter means to selectively connect the respective second plates of said first and second capacitors to said source means to receive said second reference potential signal.

Claim 13

The combination recited in claim 7, including means to provide an additional signal to said third semiconductor device control electrode so as to further boost the signal applied thereto and thereby substantially reduce the impedance of said third device with respect to that of said second device, whereby said power supply means is electrically connected to said driver means via the conduction path of said third device.

Claim 14

The combination recited in claim 11, wherein the means to provide the additional signal to said third semiconductor device control electrode includes a capacitor, said capacitor connected between said third device control electrode and clock terminal means which receives a clock signal to charge said capacitor in order to further boost the signal applied to said third device control electrode.

Claim 15

The combination recited in claim 7, wherein said first semiconductor device, said power supply means and said driver means are disposed on a single semiconductive chip.

Claim 16

A circuit for driving a semiconductor device and comprising: reference potential source means, first and second inverter means, each of said inverter means having clock terminals to receive respective multi-phase clock signals, charge storage capacitor means, said charge storage capacitor means including first and second capacitors, transmission gate means having conduction path terminals selectively connected between one plate of said first capacitor and a control electrode of said semiconductor device to be driven, said transmission gate means having a control terminal connected to a first plate of said second capacitor, said first inverter means connecting the first plate of each of said first and second capacitors to said source means during a first of said multi-phase clock signals for charging said first and second capacitors and said transmission gate means control terminal, and said second inverter means connecting second plates of each of said first and second capacitors to said source means during a second of said multi-phase clock signals for boosting the charge of said first and second capacitors and said transmission gate means control terminal for driving said transmission gate means.

Claim 17

A circuit for driving a semiconductor device and comprising: reference potential source means, first and second inverter means, each of said inverter means having clock terminals to receive respective multi-phase clock signals, charge storage capacitor means, said charge storage capacitor means including first and second capacitors, transmission gate means having conduction path terminals selectively connected between one plate of said first capacitor and a control electrode of said semiconductor device to be driven, said transmission gate means having a control terminal connected to a first plate of said second capacitor, said first inverter means connecting the first plate of each of said first and second capacitors to said source means during a first of said multi-phase clock signals for charging said first and second capacitors and said transmission gate means control terminal, and said second inverter means connecting second plates of each of said first and second capacitors to said source means during a second of said multi-phase clock signals for boosting the charge of said first and second capacitors and said transmission gate means control terminal for driving said transmission gate means.