US4047011A
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Modular apparatus for binary quotient, binary product, binary sum and binary difference generation
Assignee: Unisys Corp
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Filing: 1975-12-15
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Granted: 1977-09-06
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Expires: 1995-12-15
Abstract
Abstract Three modular arrays structured from a common module are connected together a first way to form a binary quotient by successive approximations, or a second way to form a binary product. Any one of the three modular arrays may be used to add or subtract two binary numbers. To divide, one array is utilized to generate a shift and add sequence that represents the reciprocal of the divisor, most significant bit first. As this add and shift sequence is being formed, it is, at the same time, being utilized to manipulate the dividend, thereby forming the quotient, most significant bit first. In effect, the dividend is being multiplied by the reciprocal of the divisor so as to form a product of the dividend and reciprocal of the divisor, most significant bit first. This product is actually the quotient of the dividend and divisor. The binary product of two numbers is formed, most significant bit first, by manipulating the multiplicand according to an add and shift sequence determined by use of the multiplier.
Inventors
- 👤 Walter Scott Bennett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5272; G06F7/535; G06F7/57; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3852; G06F2207/535; G06F2207/5353; G06F2207/5356
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
82 words
A high-speed divider for binary numbers, comprising: a divisor array comprising a plurality of like structured modules; a dividend array comprising a plurality of like structured modules, like the modules in said divisor array; a quotient array comprising a plurality of like structured modules, like the modules in said divisor array and said dividend array; and control means, responsive to the divisor array, for generating signals indicative of manipulative control steps for said divisor array, said dividend array, and said quotient array.
Claim 2
Dependent Claim
82 words
A high-speed divider for binary numbers, comprising: a divisor array comprising a plurality of like structured modules; a dividend array comprising a plurality of like structured modules, like the modules in said divisor array; a quotient array comprising a plurality of like structured modules, like the modules in said divisor array and said dividend array; and control means, responsive to the divisor array, for generating signals indicative of manipulative control steps for said divisor array, said dividend array, and said quotient array.
Claim 3
Dependent Claim
35 words
The high-speed divider of claim 1, wherein said divisor array comprises a serial array of like modules, the number of modules being at least one greater than the number of bit positions in the divisor.
Claim 4
Dependent Claim
99 words
The high-speed divider of claim 2 wherein each module in said serial array of modules, comprises: an upper one bit storage element; a lower one bit storage element; and a full adder connected to and receiving a first input from said upper storage element, a second input from said lower storage element, and a carry input from a less significant module, said adder supplying the sum of the first and second inputs and the carry input, if present, to the upper storage element, and supplying a carry output, if generated, to the next most significant module in the array.
Claim 5
Dependent Claim
68 words
The high-speed divider of claim 3 wherein said control means responds to output signals from the most significant module to generate a shift signal if the full adder in the most significant module would generate a carry if an addition were performed, said control means generating an add signal if the full adder in the most significant module would not generate a carry if an addition were performed.
Claim 6
Dependent Claim
38 words
The high-speed divider of claim 2 including means for loading said divisor into said divisor array so that the most significant bit of the divisor is loaded into the next to most significant module in the divisor array.
Claim 7
Dependent Claim
41 words
The high-speed divider of claim 5 wherein said means for loading loads said divisor into said divisor array so that the divisor is right justified with the binary point occurring to the left of the most significant 1 in the divisor.
Claim 8
Dependent Claim
44 words
The high-speed divider of claim 6 wherein said control means includes a binary counter connected to the output of the most significant module in said divisor array, said counter having a modulo equal to the number of modules in said quotient array, minus one.
Claim 9
Dependent Claim
116 words
A divider for dividing a dividend digital pattern by a divisor digital pattern to form a quotient digital pattern, comprising: first means for receiving a divisor digital pattern; said first means including means for manipulating a received divisor digital pattern so as to produce control signals representative of the multiplication of the received divisor digital pattern by its reciprocal; second means for receiving a dividend digital pattern; and means for applying said control signals produced by said first means to said second means; said second means including means responsive to said control signals for manipulating a received dividend in accordance with said control signals so as to produce output signals representative of said quotient digital pattern.
Claim 10
Dependent Claim
116 words
A divider for dividing a dividend digital pattern by a divisor digital pattern to form a quotient digital pattern, comprising: first means for receiving a divisor digital pattern; said first means including means for manipulating a received divisor digital pattern so as to produce control signals representative of the multiplication of the received divisor digital pattern by its reciprocal; second means for receiving a dividend digital pattern; and means for applying said control signals produced by said first means to said second means; said second means including means responsive to said control signals for manipulating a received dividend in accordance with said control signals so as to produce output signals representative of said quotient digital pattern.
Claim 11
Dependent Claim
35 words
The invention in accordance with claim 8, wherein said divisor, dividend and quotient digital patterns are each binary digit patterns, and wherein said control signals produced by said first means comprise add and shift signals.
Claim 12
Dependent Claim
22 words
The invention in accordance with claim 9, wherein said first and second means each includes a serial array of like structured modules.
Claim 13
Dependent Claim
94 words
The invention in accordance with claim 10, wherein each said module comprises: an upper one bit storage element; a lower one bit storage element; and a full adder receiving a first input from said upper storage element, a second input from said lower storage element and a carry input from a less significant module, said adder supplying the sum of the first input, second input and the carry input, if present, to said upper storage element, and supplying a carry output, if generated, to the next most significant module in a said serial array.
Claim 14
Dependent Claim
39 words
The invention in accordance with claim 11, including means for loading the divisor into the array of said first means so that the most significant digit of the divisor is loaded into the next to most significant module thereof.
Claim 15
Dependent Claim
77 words
The invention in accordance with claim 12, wherein said means for manipulating includes means responsive to output signals produced from the most significant module during manipulation of said divisor for generating a shift signal if the full adder in said most significant module would generate a carry if an addition were performed, and to generate an add signal if the full adder in the most significant module would not generate a carry if an addition were performed.
Claim 16
Dependent Claim
110 words
An arithmetic mechanism for binary numbers, comprising: a first array comprising a plurality of like structured modules; a second array comprising a plurality of like structured modules, like the modules in said first array; a third array comprising a plurality of like structured modules, like the modules in said first array and said second array; and control means, responsive to the first array, for selectively generating first or second sets of control signals indicative of manipulative control steps occurring in said first array; said control means including means for selecting between generation of said first and second sets of control signals for application to said first, second and third arrays.
Claim 17
Dependent Claim
110 words
An arithmetic mechanism for binary numbers, comprising: a first array comprising a plurality of like structured modules; a second array comprising a plurality of like structured modules, like the modules in said first array; a third array comprising a plurality of like structured modules, like the modules in said first array and said second array; and control means, responsive to the first array, for selectively generating first or second sets of control signals indicative of manipulative control steps occurring in said first array; said control means including means for selecting between generation of said first and second sets of control signals for application to said first, second and third arrays.
Claim 18
Dependent Claim
21 words
The invention in accordance with claim 14, wherein said first array of like structured modules comprises a serial array of modules.
Claim 19
Dependent Claim
42 words
The invention in accordance with claim 15, including means for loading a first plurality of binary digits into said serial array of modules so that the most significant bit is loaded into the next to most significant module in said serial array.
Claim 20
Dependent Claim
100 words
The arithmetic mechanism for binary numbers of claim 15 wherein each module in said serial array of modules comprises: an upper one bit storage element; a lower one bit storage element; and a full adder receiving a first input from said upper storage element, a second input from said lower storage element, and a carry input from a less significant module, said adder supplying the sum of the first input, second input and the carry input, if present, to the upper storage element, and supplying a carry output, if generated, to the next most significant module in said serial array.
Claim 21
Dependent Claim
89 words
The arithmetic mechanism for binary numbers of claim 17 wherein said control means is constructed and arranged so that when generating said first set of control signals, it responds to output signals from the most significant module in said first array to generate a shift signal if the full adder in the most significant module would generate a carry if an addition were performed and to generate an add signal if the full adder in the most significant module would not generate a carry if an addition were performed.
Claim 22
Dependent Claim
49 words
The invention in accordance with claim 17, wherein said control means further includes means for placing and maintaining a binary one in the lower one bit storage element in the most significant module in said serial array when said control means is generating said second set of control signals.
Claim 23
Dependent Claim
30 words
The invention in accordance with claim 14, including means for loading at least one of said first, second and third arrays with an augend-addend pair for producing the sum thereof.
Claim 24
Dependent Claim
30 words
The invention in accordance with claim 14, including means for loading at least one of said first, second and third arrays with a minuend-subtrahend pair for producing the difference thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-05 | 1981-03-07 | 1981-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-05 | 1985-03-07 | 1985-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-05 | 1989-03-07 | 1989-09-06 | $7700.00 | Window Closed / Lapsed |