US4044345A — Method for addressing X-Y matrix display cells

Claim 1

Independent Claim 214 words

A matrix addressing method for a group of X-Y matrix display cells having an X i -Y j two-dimensional matrix electrode structure (where i equals 1,2,3, . . . , M, and j equals 1,2,3, . . . , N) during an N time frame period comprising the steps of: applying an X i -electrode voltage e Xi having a binary value of one or zero to the 1,2,3, . . . , M electrodes in such a manner that predetermined number of binary is applied during each time frame; applying a Y j -electrode voltage e Yj having a binary value of one or zero sequentially to the 1,2,3, . . . , N Y j electrodes in such a manner that a binary one is only applied to the first electrode during the first time frame, a binary one is only applied to the second electrode during the second time frame, a binary one is only applied to the third electrode during the third time frame, . . . , and a binary one is only applied to the Nth electrode during the Nth time frame; and addressing matrix display cells P ij in response to the timing at which the electrode voltages e Xi and e Yj assume individual binary states.

Claim 2

Dependent Claim 214 words

A matrix addressing method for a group of X-Y matrix display cells having an X i -Y j two-dimensional matrix electrode structure (where i equals 1,2,3, . . . , M, and j equals 1,2,3, . . . , N) during an N time frame period comprising the steps of: applying an X i -electrode voltage e Xi having a binary value of one or zero to the 1,2,3, . . . , M electrodes in such a manner that predetermined number of binary is applied during each time frame; applying a Y j -electrode voltage e Yj having a binary value of one or zero sequentially to the 1,2,3, . . . , N Y j electrodes in such a manner that a binary one is only applied to the first electrode during the first time frame, a binary one is only applied to the second electrode during the second time frame, a binary one is only applied to the third electrode during the third time frame, . . . , and a binary one is only applied to the Nth electrode during the Nth time frame; and addressing matrix display cells P ij in response to the timing at which the electrode voltages e Xi and e Yj assume individual binary states.

Claim 3

Dependent Claim 86 words

A matrix addressing method as claimed in claim 1 further comprising the steps of setting the Y j - electrode voltage e Yj to a constant potential V 2 when e Yj is a binary one and to a constant potential V 1 when e Yj is a binary zero and setting the X i -electrode voltage e Xi to a constant potential V 2 when e Xi is a binary one and to a constant potential V 1 when e Xi is a binary zero.

Claim 4

Dependent Claim 118 words

A matrix addressing method as claimed in claim 1 further comprising the steps of setting, when n=1, the Y j -electrode voltage e Yj to a constant potential V 2 when e Yj is a binary one and to a constant potential V 1 when e Yj is a binary zero and setting the X i -electrode voltage e Xi to a constant potential V 4 when e Xi is a binary one and to a constant potential V 3 when e Xi is a binary zero and establishing the relationship among V 1 , V 2 , V 3 and V 4 as follows: V.sub.1 + (V.sub.2 - V.sub.1) /N = V.sub.4 - (V.sub.3 31 V.sub.4) /N

Claim 5

Dependent Claim 104 words

A matrix addressing method as claimed in claim 1 further comprising the steps of setting when N> n ≧ 2, the Y j -electrode voltage e Yj to a potential V O + ΔV[1 - (1 N) ] when e Yj is a binary one and to a potential V 0 + ΔV[1- (ΔV/N)] when e Yj is a binary zero and setting the X i - electrode voltage e Xi to a potential V 0 + Δ V([1 - (n/N) ] when e Xi is a binary one and to a potential V 0 + ΔV(n/N) when e Xi is a binary zero.

Claim 6

Dependent Claim 20 words

A matrix addressing method as claimed in claim 1 wherein the group of matrix display cells are liquid crystal cells.

Claim 7

Dependent Claim 19 words

A matrix addressing method as claimed in claim 1 wherein the group of matrix display cells are electroluminescent cells.

Claim 8

Dependent Claim 221 words

A matrix addressing system comprising: means for converting an analogue signal of an N level to a binary signal l = log 2 N with an A/D convertor and for writing M signals of each predetermined sampling interval in a l -bit and M word register memory; means for repeatedly counting up from 0 to N-1 with a N progress l bit counter; means for sequentially comparing the data of said l bit shift register and the data of said l bit counter at a word unit in parallel for M words and writing "1" when they coincide and writing "0" when they do not coincide in the M bit shift register; means for maintaining the data in a M bit latch array after comparing and writing the data for M words; means for applying to M of the X-electrodes a first predetermined potential in the case of "1" and a second predetermined potential in the case of "0" depending upon the data of the latch array; means for converting the binary output of the l bit counter to an N binary output with a decoder; and means for applying to N of Y-electrodes a third predetermined potential in the case of "1" and a fourth predetermined potential in the case of "0" depending upon the data of the decoder output.

Claim 9

Dependent Claim 221 words

A matrix addressing system comprising: means for converting an analogue signal of an N level to a binary signal l = log 2 N with an A/D convertor and for writing M signals of each predetermined sampling interval in a l -bit and M word register memory; means for repeatedly counting up from 0 to N-1 with a N progress l bit counter; means for sequentially comparing the data of said l bit shift register and the data of said l bit counter at a word unit in parallel for M words and writing "1" when they coincide and writing "0" when they do not coincide in the M bit shift register; means for maintaining the data in a M bit latch array after comparing and writing the data for M words; means for applying to M of the X-electrodes a first predetermined potential in the case of "1" and a second predetermined potential in the case of "0" depending upon the data of the latch array; means for converting the binary output of the l bit counter to an N binary output with a decoder; and means for applying to N of Y-electrodes a third predetermined potential in the case of "1" and a fourth predetermined potential in the case of "0" depending upon the data of the decoder output.

Claim 10

Dependent Claim 32 words

A matrix addressing system according to claim 7 wherein said first predetermined potential is equal to said third predetermined potential and said second predetermined potential is equal to said fourth predetermined potential.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1980-08-22	1981-02-21	1981-08-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1984-08-22	1985-02-21	1985-08-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1988-08-22	1989-02-21	1989-08-23	$7700.00	Window Closed / Lapsed

Method for addressing X-Y matrix display cells

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