US3824003A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Liquid crystal display panel
Assignee: Raytheon Co
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Filing: 1973-05-07
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Granted: 1974-07-16
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Expires: 1993-05-07
Abstract
Abstract In a liquid crystal matrix display panel for line-at-a-time driving at TV rate, an array of field effect transistor switches enable inputs to respective storage capacitors thereby providing storage of signals for a sufficient time for the liquid crystal material to respond. The transistor''s drain pad also serves as one plate of the associated storage capacitor and a portion of its gate electrode is effectively the second plate, thereby minimizing the number of drive lines required and facilitating the fabrication of a practical device using state-of-the-art thin film transistor technology.
Inventors
- 👤 N Koda
- 👤 L Lipton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:48
CPC Classifications
H; H10; H10P; H10P95/00; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10D; H10D99/00; G02F1/136213
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
178 words
A matrix display panel adaptable for line-at-a-time addressing comprising: a substrate having fabricated on a surface thereof a transistor array including a plurality of gate lines and a plurality of source lines intersecting said gate lines; a plurality of row generators, one for each of said gate lines, each row generator being directly coupled to its associated gate line for enabling a row of transistors within said transistor array; a plurality of column generators, one for each of said source lines, each of said column generators being directly coupled to its associated source line for providing an input signal to an enabled transistor within said transistor array; a plurality of drain pads, one for each transistor within said transistor array, each of said drain pads being capacitively coupled to the gate line associated with its particular transistor; a top plate having a transparent conductor; and liquid crystal material sandwiched between said transistor array and said transparent conductor, and having optical properties alterable in response to the electrical field between each one of said drain pads and said conductor.
Claim 2
Dependent Claim
178 words
A matrix display panel adaptable for line-at-a-time addressing comprising: a substrate having fabricated on a surface thereof a transistor array including a plurality of gate lines and a plurality of source lines intersecting said gate lines; a plurality of row generators, one for each of said gate lines, each row generator being directly coupled to its associated gate line for enabling a row of transistors within said transistor array; a plurality of column generators, one for each of said source lines, each of said column generators being directly coupled to its associated source line for providing an input signal to an enabled transistor within said transistor array; a plurality of drain pads, one for each transistor within said transistor array, each of said drain pads being capacitively coupled to the gate line associated with its particular transistor; a top plate having a transparent conductor; and liquid crystal material sandwiched between said transistor array and said transparent conductor, and having optical properties alterable in response to the electrical field between each one of said drain pads and said conductor.
Claim 3
Dependent Claim
26 words
The panel of claim 1 wherein each of said gate lines is of a relatively constant width substantially equal to the width of said drain pads.
Claim 4
Dependent Claim
16 words
The panel of claim 1 wherein said drain pads are formed of a reflective metal material.
Claim 5
Dependent Claim
125 words
An integrated transistor array for matrix addressing of a liquid crystal material, said array comprising: a substrate having a planar surface; a plurality of gate lines formed on said substrate surface, said lines being oriented in a first direction; a layer of insulating material deposited over said substrate surface and said gate line; a layer of semiconductor material deposited over said insulating layer; a plurality of source lines oriented in a second direction intersecting said first direction, said source lines being formed on said semiconductor layer; and a plurality of drain pads also formed on said semiconductor layer, one such drain pad being located in the vicinity of each intersection of a gate line with a source line and capacitively coupled to said gate line.
Claim 6
Dependent Claim
125 words
An integrated transistor array for matrix addressing of a liquid crystal material, said array comprising: a substrate having a planar surface; a plurality of gate lines formed on said substrate surface, said lines being oriented in a first direction; a layer of insulating material deposited over said substrate surface and said gate line; a layer of semiconductor material deposited over said insulating layer; a plurality of source lines oriented in a second direction intersecting said first direction, said source lines being formed on said semiconductor layer; and a plurality of drain pads also formed on said semiconductor layer, one such drain pad being located in the vicinity of each intersection of a gate line with a source line and capacitively coupled to said gate line.
Claim 7
Dependent Claim
73 words
A liquid crystal elemental cell adapted for integration into an addressable display, said cell comprising: a thin film transistor having gate, source and drain electrodes; a thin film capacitor comprising opposed portions of said gate and drain electrodes; a transparent conduCtor spaced from said thin film transistor; and liquid crystal material sandwiched between said transistor and said conductor and responsive to the electrical field established between said drain electrode and said transparent conductor.
Claim 8
Dependent Claim
73 words
A liquid crystal elemental cell adapted for integration into an addressable display, said cell comprising: a thin film transistor having gate, source and drain electrodes; a thin film capacitor comprising opposed portions of said gate and drain electrodes; a transparent conduCtor spaced from said thin film transistor; and liquid crystal material sandwiched between said transistor and said conductor and responsive to the electrical field established between said drain electrode and said transparent conductor.
Claim 9
Dependent Claim
25 words
The cell of claim 5 wherein said drain electrode is of a reflective metallic material whereby a reflective mode of display operation may be realized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-15 | 1978-01-14 | 1978-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-15 | 1982-01-14 | 1982-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-15 | 1986-01-14 | 1986-07-16 | $7700.00 | Window Closed / Lapsed |