Driving arrangement for liquid crystal displays

Claim 2

A driving arrangement for a liquid crystal display comprising control circuit means formed from complementary field effect transistors for applying an alternating driving voltage to said liquid crystal display.

Claim 3

A driving arrangement as recited in claim 1, wherein said liquid crystal display is the display dial of an electronic watch.

Claim 4

A driving arrangement as recited in claim 1, wherein said liquid crystal display includes a segmented electrode, a common electrode in spaced relation to said segmented electrode and liquid crystal material between said segmented and common electrodes; decoder means for producing a substantially DC driving signal associated with each segment of said segmented electrode; said control circuit means including select gate means associated with each of said segmented electrode segments, means for applying both the associated DC driving voltage and inverse thereof to said select gate means; means for applying an AC control signal to said select gate means for controlling the transmission thereof so that said select gate means alternately transmits said driving signal and the inverse thereof to the associated segmented electrode segment in response to said AC control signal, and means for applying the inverse of said AC control signal to said common electrode.

Claim 5

A driving arrangement as recited in claim 3, wherein said control circuit means is adapted so that the AC signal applied to each segment of said segmented electrode to be displayed is out of phase with the signal applied to said common elecrode while the AC signal applied to each segment of said segmented electrode which is not to be displayed is in phase with the signal applied to said common electrode.

Claim 6

A driving arrangement as recited in claim 3, wherein said select gate means includes first and second transmission gates each formed from a pair of complementary field effect transistors, the associated DC driving signal being applied to the source-drain path of said first transmission gate and the inverse of said DC driving signal being applied to the source-drain path of said second transmission gate, said AC control signal being applied to one of the gate electrodes of each of said first and second transmission gates and the inverse of said AC control signal being applied to the other gate electrode of each of said transmission gates.

Claim 7

A driving arrangement as recited in claim 3, wherein said select gate means includes first and second AND gate means, said first AND gate means having as its inputs the associated DC driving signal and said AC control signal, said second AND gate means having as its inputs the inverse of said DC driving signal and the inverse of said AC control signal; and an OR gate interconnecting the outputs of said first and second AND gate means and the associated segments of said segmented electrode.

Claim 8

A driving arrangement for liquid crystal display panels having a segmented electrode, a common electrode, and liquid crystal material intermediate said segmented and common electrode comprising decoder means for producing DC driving signals associated with each segment of said segmented electrode; control circuit means having select gate means associated with each of said DC driving signals; means for applying said DC driving signal and the inverse thereof to each of said select gate means; means for applying an AC control signal to said select gate means so that said DC driving signal and the inverse thereof are alternately applied to the associated segment of said segmented electrode in response to said AC control signal, and means for applying the inverse of said AC control signal to said common electrode.

Claim 9

A driving arrangement for liquid crystal display panels having a segmented electrode, a common electrode, and liquid crystal material intermediate said segmented and common electrode comprising decoder means for producing DC driving signals associated with each segment of said segmented electrode; control circuit means having select gate means associated with each of said DC driving signals; means for applying said DC driving signal and the inverse thereof to each of said select gate means; means for applying an AC control signal to said select gate means so that said DC driving signal and the inverse thereof are alternately applied to the associated segment of said segmented electrode in response to said AC control signal, and means for applying the inverse of said AC control signal to said common electrode.

Claim 10

A driving arrangement as recited in claim 7, wherein said control circuit means is formed from complementary field effect transistors.

Claim 11

A driving arrangement as recited in claim 8, wherein said liquid crystal display is the display dial of an electronic watch.

Claim 12

A driving arrangement as recited in claim 7, wherein said control circuit means is adapted so that the AC signal applied to each segment of said segmented electrode to be displayed is out of phase with the signal applied to said common electrode while the AC signal applied to each segment of said segmented electrode which is not to be displayed is in phase with the signal applied to said common electrode.

Claim 13

A driving arrangement as recited in claim 7, wherein said select gate means includes first and second transmission gates each formed from a pair of complementary field effect transistors, the associated DC driving signal being applied to the source-drain path of said first transmission gate and the inverse of said DC driving signal being applied to the source-drain path of said second transmission gate, said AC control signal being applied to one of the gate electrodes of each of said first and second transmission gates and the inverse of said AC control signal being applied to the other gate electrode of each of said transmission gates.

Claim 14

A driving arrangement as recited in claim 7, wherein said select gate means includes first and second AND gate means, said first AND gate means having as its inputs the associated DC driving signal and said AC control signal, said second AND gate means having as its inputs the inverse of said DC driving signal and the inverse of said AC control signal; and an OR gate interconnecting the outputs of said first and second AND gate means and the associated segments of said segmented electrode.