Image or segment pattern forming X-Y matrix addressing method

Claim 2

An X-Y matrix addressing method in which M numbers of electrodes X1 through XM are arranged in an X column, and N numbers of electrodes Y1 through YN are arranged in a Y row, intersecting perpendicularly with the X-column electrodes, comprising the steps of: applying scanning voltages eY1 through eYN to the N number of Yrow electrodes at a cycle T seconds; applying signal voltages eX1 through eXM to the M number of Xcolumn electrodes; applying a voltage eXi - eYj to a matrix cell Pij formed in the region where an arbitrary one Xi of the M number of X-column electrodes intersects with an arbitrary one Yj of the N number of Y-row electrodes, in response to the timings of the bit state of the signal voltage and the bit state of the scanning voltage, thereby causing the X-Y matrix cells to exhibit a response in the form of an image or segment pattern; and, determining the bit states of the scanning voltage eYj and of the signal voltage eXi so that the voltage eYj assumes the bit state 1 for the period of (T/N) seconds at the cycle T and the bit state 0 for the rest of the period T - (T/N) seconds, and the voltage eXi assumes the bit state 1 or 0 according to the bit state matrix cell Sij of an arbitrary signal, the scanning voltage eYj is EOY - (V1/2) for the first half of the bit state 1 of the scanning voltage eYj and is EOY + (V1/2) for the latter half of the bit state 1 where EOY stands for an arbitrary potential value, and V1 for a voltage with an arbitrary polarity and value, and further the scanning voltage eYj is EOY for the period where the bit state of the scanning voltage eYj is 0, while, the signal voltage eXi is EOX + (V2/2) for the first half of the bit state 1 of the signal voltage eXi and is EOX - (V2/2) for the latter half of the bit state 1 where EOX stands for an arbitrary potential value, and V2 for a voltage with an arbitrary polarity and value.

Claim 3

An X-Y matrix addressing method as claimed in claim 1 further comprising the step of making the voltage V1 nearly equal to Square Root N . V2.

Claim 4

An X-Y matrix addressing method in which M numbers of electrodes X1 through XM are arranged in an X column, and N numbers of electrodes Y1 through YN are arranged in a Y row, intersecting perpendicularly with the X-column electrodes, comprising the steps of: applying scanning voltages eY1 through eYN to the N number of Y-row electrodes at a cycle T seconds; applying signal voltages eX1 through eXM to the M number of X-column electrodes; applying a voltage eXi - eYj to a matrix cell Pij formed in the region where an arbitrary one Xi of the M number of X-column electrodes intersects with an arbitary one Yj of the N number of Y-row electrodes, in response to the timings of the bit state of the signal voltage and the bit state of the scanning voltage, thereby causing the X-Y matrix cells to exhibit a response in the form of an image or segment pattern; and, determining the bit states of the scanning voltage eYj and of the signal voltage eXi so that the voltage eYj assumes the bit state 1 for the period of (T/N) seconds at the cycle T and the bit state 0 for the rest of the period T - (T/N) seconds, and the voltage eXi assumes the bit state 1 or 0 according to the bit state matrix cell Sij of an arbitrary signal, the scanning voltage eYj occurs at two potentials EOY - (V1/2) and EOY + (V1/2) where EOY stands for an arbitrary potential value, and V1 for a voltage with an arbitrary polarity and value alternately n times repeatedly at the cycle (T/n.N) seconds where n is an integer excepting 0 and 1, in a square waveform beginning with EOY - (V1/2), during the bit state 1 of the scanning voltage eYj, or the scanning voltage eYj occurs at a potential EOY during the bit state 0 of the scanning voltage eYj, while the signal voltage eXi occurs at two potentials EOX + (V2/2) and EOX - (V2/2) where EOX stands for an arbitrary potential value, and V2 for a voltage with an arbitrary polarity and value alternately n times repeatedly at the cycle (T/n . N) seconds where n is an integer excepting 0 and 1, in a square waveform beginning with EOX + (V2/2), during the bit state 1 of the signal voltage eXi, or the signal voltage eXi occurs at two potentials EOX - (V2/2) and EOX + (V2/2) alternately at the cycle (T/n . N) seconds, in a square waveform beginning with EOX - (V2/2), during the bit state 0 of the signal voltage eXi.

Claim 5

An X-Y matrix addressing method in which M numbers of electrodes X1 through XM are arranged in an X column, and N numbers of electrodes Y1 through YN are arranged in a Y row, intersecting perpendicularly with the X-column electrodes, comprising the steps of: applying scanning voltages eY1 through eYN to the N number of Y-row electrodes at a cycle T seconds; applying signal voltages eX1 through eXM to the M number of X-column electrodes; applying a voltage eXi - eYj to a matrix cell Pij formed in the region where an arbitrary one Xi of the M number of X-column electrodes intersects with an arbitary one Yj of the N number of Y-row electrodes, in response to the timings of the bit state of the signal voltage and the bit state of the scanning voltage, thereby causing the X-Y matrix cells to exhibit a response in the form of an image or segment pattern; and, determining the bit states of the scanning voltage eYj and of the signal voltage eXi so that the voltage eYj assumes the bit state 1 for the period of (T/N) seconds at the cycle T and the bit state 0 for the rest of the period T - (T/N) seconds, and the voltage eXi assumes the bit state 1 or 0 according to the bit state matrix cell Sij of an arbitrary signal, the scanning voltage eYj occurs at two potentials EOY - (V1/2) and EOY + (V1/2) where EOY stands for an arbitrary potential value, and V1 for a voltage with an arbitrary polarity and value alternately n times repeatedly at the cycle (T/n.N) seconds where n is an integer excepting 0 and 1, in a square waveform beginning with EOY - (V1/2), during the bit state 1 of the scanning voltage eYj, or the scanning voltage eYj occurs at a potential EOY during the bit state 0 of the scanning voltage eYj, while the signal voltage eXi occurs at two potentials EOX + (V2/2) and EOX - (V2/2) where EOX stands for an arbitrary potential value, and V2 for a voltage with an arbitrary polarity and value alternately n times repeatedly at the cycle (T/n . N) seconds where n is an integer excepting 0 and 1, in a square waveform beginning with EOX + (V2/2), during the bit state 1 of the signal voltage eXi, or the signal voltage eXi occurs at two potentials EOX - (V2/2) and EOX + (V2/2) alternately at the cycle (T/n . N) seconds, in a square waveform beginning with EOX - (V2/2), during the bit state 0 of the signal voltage eXi.

Claim 6

An X-Y matrix addressing as claimed in claim 3 further comprising the step of making the voltage V1 nearly equal to Square Root N . V2.

Claim 7

An X-Y matrix addressing method in which M numbers of electrodes X1 through XM are arranged in an X column, and N numbers of electrodes Y1 through YN are arranged in a y row, intersecting perpendicularly with the X-column electrodes, comprising the steps of: applying scanning voltages eY1 through eYN to the N number of Y-row electrodes at the cycle T second; applying signal voltages eX1 through eXM to the M number of X-column electrodes; applying a voltage eXi - eYj to a matrix cell Pij formed in the region where an arbitrary one Xi of the M number of X-column electrodes intersects with an arbitrary one Yj of the N number of Y-row electrodes, in response to the timings of the bit state of the signal voltage and the bit state of the scanning voltage, thereby causing the X-Y matrix cells to exhibit a response in the form of an image or segment pattern; and, determining the bit states of the scanning voltage eYj and of the signal voltage eXi so that the voltage eYj assumes the bit state 1 for the period of (T/N) seconds at the cycle T and the bit state 0 for the rest of the period T - (T/N) seconds, and the voltage eXi assumes the bit state 1 or 0 according to the bit state matrix cell Sij of an arbitrary signal, the scanning voltage eYj occurs at two potentials EOY - (V1/2) and EOY + (V1/2) where EOY stands for an arbitrary potential value, and V1 for a voltage with an arbitrary polarity and value alternately n times repeatedly at the cycle (T/n . N) seconds where n is an integer excepting 0 and 1, under the condition that the signal voltage eXi assumes a bit state including 1 and 0 or an arbitrary intermediate bit state Alpha /n (where 0 < or = Alpha . < or = 1), or the scanning voltage eYj occurs at EOY when its bit state is 0, while the signal voltage eXi occurs at two potentials EOX + (V2/2) and EOX - (V2/2) where EOX stands for an arbitrary potential value, and V2 for a voltage with an arbitrary polarity and value alternately for (T/n . N) Alpha seconds repeatedly at the cycle (T/n . N) seconds, and for the rest of the time

Claim 8

An X-Y matrix addressing method in which M numbers of electrodes X1 through XM are arranged in an X column, and N numbers of electrodes Y1 through YN are arranged in a y row, intersecting perpendicularly with the X-column electrodes, comprising the steps of: applying scanning voltages eY1 through eYN to the N number of Y-row electrodes at the cycle T second; applying signal voltages eX1 through eXM to the M number of X-column electrodes; applying a voltage eXi - eYj to a matrix cell Pij formed in the region where an arbitrary one Xi of the M number of X-column electrodes intersects with an arbitrary one Yj of the N number of Y-row electrodes, in response to the timings of the bit state of the signal voltage and the bit state of the scanning voltage, thereby causing the X-Y matrix cells to exhibit a response in the form of an image or segment pattern; and, determining the bit states of the scanning voltage eYj and of the signal voltage eXi so that the voltage eYj assumes the bit state 1 for the period of (T/N) seconds at the cycle T and the bit state 0 for the rest of the period T - (T/N) seconds, and the voltage eXi assumes the bit state 1 or 0 according to the bit state matrix cell Sij of an arbitrary signal, the scanning voltage eYj occurs at two potentials EOY - (V1/2) and EOY + (V1/2) where EOY stands for an arbitrary potential value, and V1 for a voltage with an arbitrary polarity and value alternately n times repeatedly at the cycle (T/n . N) seconds where n is an integer excepting 0 and 1, under the condition that the signal voltage eXi assumes a bit state including 1 and 0 or an arbitrary intermediate bit state Alpha /n (where 0 < or = Alpha . < or = 1), or the scanning voltage eYj occurs at EOY when its bit state is 0, while the signal voltage eXi occurs at two potentials EOX + (V2/2) and EOX - (V2/2) where EOX stands for an arbitrary potential value, and V2 for a voltage with an arbitrary polarity and value alternately for (T/n . N) Alpha seconds repeatedly at the cycle (T/n . N) seconds, and for the rest of the time

Claim 9

An X-Y matrix addressing method as claimed in claim 5 further comprising the step of making the voltage V1 nearly equal to Square Root N. V2.