Block oriented random access memory

Claim 2

An integrated circuit for use in a block oriented random access memory, the integrated circuit comprising: a memory block for storing a plurality of words, the memory block comprising an N × M memory array having N words of M bits each; terminal means for receiving block select signals; sequential addressing means associated with the memory block for sequentially addressing each word of the memory block in a predetermined order when the memory block is selected, the sequential addressing means comprising an N bit shift register wherein each bit of the N bit shift register is connected to one of the N words of the N × M memory array and wherein each word of the N × M memory array is addressed when the bit of the N bit shift register to which it is connected attains a first level;

Claim 3

loading means for loading a signal of the first level in one end of the N bit shift register when the memory block is selected, and wherein the shift register is adapted to receive clock signals and to shift sequentially the signal of the first level from the one end of the N bit shift register to an opposite end, and then off the end, in response to the clock signals, whereby each word of the memory block is sequentially addressed in a predetermined order; data input means for entering data into each addressed word in response to an input signal; and data output means for reading out data from each addressed word in response to an output signal.

Claim 4

loading means for loading a signal of the first level in one end of the N bit shift register when the memory block is selected, and wherein the shift register is adapted to receive clock signals and to shift sequentially the signal of the first level from the one end of the N bit shift register to an opposite end, and then off the end, in response to the clock signals, whereby each word of the memory block is sequentially addressed in a predetermined order; data input means for entering data into each addressed word in response to an input signal; and data output means for reading out data from each addressed word in response to an output signal.

Claim 5

The integrated circuit of claim 1 wherein the data input means and the data output means comprise: an M bit latch connected to the N × M memory array; and an M bit shift register connected to the M bit latch.

Claim 6

An integrated circuit for use in a block oriented random access memory, the integrated circuit comprising: S memory blocks, wherein S is an integer greater than zero, each memory block for storing a plurality of words, wherein each memory block comprises an N/S × M memory array having N/S words of M bits each; terminal means for receiving signals which identify a selected memory block, the terminal means including log 2 S terminals for receiving log 2 S signals which identify a selected memory block; sequential addressing means associated with each memory block for sequentially addressing each word of the memory block in a predetermined order when enabled, the sequential addressing means comprising S shift registers of N/S bits each, each N/S bit shift register being associated with one of the S memory blocks, wherein each bit of the N/S bit shift register is connected to one of the N/S words of the N/S × M memory array and wherein each word of the N/S × M memory array is addressed when the bit of the N/S bit shift register to which it is connected attains a first level; enabling means connected to the terminal means for enabling a selected N/S bit shift register; and loading means for loading the signal of the first level in one end of the proper N/S bit shift register when a memory block is selected, wherein the N/S bit shift register is adapted to receive clock signals and to shift sequentially the signal of the first level from the one end of the shift register to an opposite end, and then off, in response to the clock signals whereby each word of the selected memory block is sequentially addressed in a predetermined order.

Claim 7

An integrated circuit for use in a block oriented random access memory, the integrated circuit comprising: S memory blocks, wherein S is an integer greater than zero, each memory block for storing a plurality of words, wherein each memory block comprises an N/S × M memory array having N/S words of M bits each; terminal means for receiving signals which identify a selected memory block, the terminal means including log 2 S terminals for receiving log 2 S signals which identify a selected memory block; sequential addressing means associated with each memory block for sequentially addressing each word of the memory block in a predetermined order when enabled, the sequential addressing means comprising S shift registers of N/S bits each, each N/S bit shift register being associated with one of the S memory blocks, wherein each bit of the N/S bit shift register is connected to one of the N/S words of the N/S × M memory array and wherein each word of the N/S × M memory array is addressed when the bit of the N/S bit shift register to which it is connected attains a first level; enabling means connected to the terminal means for enabling a selected N/S bit shift register; and loading means for loading the signal of the first level in one end of the proper N/S bit shift register when a memory block is selected, wherein the N/S bit shift register is adapted to receive clock signals and to shift sequentially the signal of the first level from the one end of the shift register to an opposite end, and then off, in response to the clock signals whereby each word of the selected memory block is sequentially addressed in a predetermined order.