US3614751A
Expired / Lapsed
US
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Memory circuit
Assignee: Hitachi Ltd
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Filing: 1969-09-18
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Granted: 1971-10-19
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Expires: 1989-09-18
Abstract
Abstract A memory circuit comprising counters of which the number of bits is equal to that of information, each one of the said counters corresponding to each address, and a single such counter common to all the addresses, wherein the said counters are advanced in synchronism with clock pulses, the counter corresponding to the address where information is to be written is set to a particular numerical representation at such a clock position that the contents of the write register and common counter are in conformity with each other, and the content of the common counter is read out at such a clock position that the address counters represent a particular number and is then transferred to a readout register.
Inventors
- 👤 Hiroshi Narisawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:08
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04; G11C13/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
159 words
AN INFORMATION STORAGE APPARATUS COMPRISING: FIRST MEANS FOR GENERATING A PLURALITY OF PULSES; A FIRST N-bit counter, responsive to the output of said first means, for counting the pulses generated by said first means; a plurality of memory circuits, each having a second N-bit counter which is responsive to the output of said first means, for counting the pulses generated thereby in synchronism with said first N-bit counter; second means, responsive to the output of said first N-bit counter, for setting one of said second N-bit counters, wherein information is to be stored, at a first predetermined count when the output of said first N-bit counter reaches a first preselected sum; and third means, for reading out the contents of one of said second N-bit counters in one of said memory circuits including means, responsive to a second predetermined count stored in said one of said second N-bit counters for transferring out the contents of said first N-bit counter.
Claim 2
Dependent Claim
159 words
AN INFORMATION STORAGE APPARATUS COMPRISING: FIRST MEANS FOR GENERATING A PLURALITY OF PULSES; A FIRST N-bit counter, responsive to the output of said first means, for counting the pulses generated by said first means; a plurality of memory circuits, each having a second N-bit counter which is responsive to the output of said first means, for counting the pulses generated thereby in synchronism with said first N-bit counter; second means, responsive to the output of said first N-bit counter, for setting one of said second N-bit counters, wherein information is to be stored, at a first predetermined count when the output of said first N-bit counter reaches a first preselected sum; and third means, for reading out the contents of one of said second N-bit counters in one of said memory circuits including means, responsive to a second predetermined count stored in said one of said second N-bit counters for transferring out the contents of said first N-bit counter.
Claim 3
Dependent Claim
45 words
An apparatus according to claim 1, further including a write register connected to said second means for supplying said first predetermined count to said first means and wherein said third means comprises a read-out register coupled to said transferring means and said first N-bit counter.
Claim 4
Dependent Claim
53 words
An apparatus according to claim 2, wherein each of said memory circuits further includes a first logic circuit responsive to the Output of said second means and a signal representative of the address of that particular memory circuit for delivering a predetermined count set signal to the second N-bit counter within said memory.
Claim 5
Dependent Claim
86 words
An apparatus according to claim 2, wherein each memory circuit includes a second logic circuit responsive to the storage of said second predetermined count in the second N-bit counter therein for providing an output signal upon the storage of said second predetermined count and a third logic circuit, responsive to a signal representative of the address of that particular memory circuit, the read-out signal, the output of said second logic circuit, for enabling said transferring means to read out the contents of said first N-bit counter.
Claim 6
Dependent Claim
87 words
An apparatus according to claim 3, wherein each memory circuit includes a second logic circuit, responsive to the storage of said second predetermined count in the second N-bit counter therein for providing an output signal upon the storage of said second predetermined count and a third logic circuit responsive to a signal representative of the address of that particular memory circuit, a read-out signal and the output of said second logic circuit, for enabling said transferring means to read out the contents of said first N-bit counter.
Claim 7
Dependent Claim
54 words
An apparatus according to claim 5, wherein said transferring means comprises an N-plurality of AND gates each of which is coupled to the output of said third logic circuit and are respectively connected to the outputs of said first N-bit counter, the outputs of said AND gates being respectively connected to said read-out register.
Claim 8
Dependent Claim
35 words
An apparatus according to claim 6, wherein each of said first, second and third logic circuits comprises a NAND gate, the outputs of which are respectively connected through inverter circuits for inverting the outputs thereof.
Claim 9
Dependent Claim
16 words
An apparatus according to claim 4, wherein said first and second predetermined counts are the same.
References Cited (Backward Citations)
US3274566A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |