Monolithic NTDS driver and receiver

Claim 2

A level shifting network comprising: a negative voltage logic level system having an input and an output; a driver network including an input and an output for converting positive voltage logic levels to the negative voltage logic levels of said negative voltage logic level system comprising first and second transistor means connected to said driver input, third and fourth transistor means connected to said first and second transistor means respectively for outputting at said driver output negative voltage logic levels to said negative voltage logic level system, whereby in response to a low positive voltage logic level signal at said driver input, said driver output is at a low negative voltage logic level and in response to a high positive voltage logic level signal at said driver input, said driver output is at a high negative voltage logic level; a receiver network including an output for converting the negative voltage logic levels of said negative voltage logic level system to positive voltage logic levels comprising a differential amplifier having a first input connected to the output of said negative voltage logic level system, a second input, and an output, said receiver network further including a fifth transistor means connected to the output of said differential amplifier, sixth and seventh transistor means connected to said fifth transistor means for outputting positive voltage logic levels at said receiver output, whereby in response to a low negative voltage logic level and in response to a high negative voltage logic level signal at said first input, said receiver output is at a high positive voltage logic level.

Claim 3

The network of claim 1 wherein said first transistor means has a base, an emitter and a collector, said first transistor means base being connected to said driver input, said first transistor means collector being connected to said third transistor means; said second transistor means having a base, an emitter and a collector, said second transistor means emitter being connected to said driver input, said second transistor means collector being connected to said fourth transistor means; said first transistor means being conducting in response to low positive voltage logic level signals at said driver input and being non-conducting in response to high positive voltage logic level signals at said driver input; said second transistor means being conducting in response to high positive voltage logic level signals at said driver input and being non-conducting in response to low positive voltage logic level signals at said driver input.

Claim 4

The network of claim 2 wherein: said third transistor means has a base, an emitter and a collector; said first transistor means collector being connected to said third transistor means base; said fourth transistor means has a base, an emitter and a collector; said second transistor means collector being connected to said fourth transistor means base.

Claim 5

The network of claim 3 wherein: said fifth transistor means includes a base, an emitter and a collector; said fifth transistor means base being connected to said differential amplifier output; said sixth transistor means includes a base, an emitter, and a collector, said sixth transistor means base being connected to said fifth transistor emitter; said seventh transistor means includes a base, an emitter, and a collector, said seventh transistor means base being connected to said fifth transistor means collector.

Claim 6

The network of claim 4 wherein said receiver network includes a constant current source connected to said differential amplifier.

Claim 7

A level shifting network for shifting positive voltage logic levels to negative voltage logic levels comprising: an input and an output; first and second transistor means connected to said input for receiving positive voltage logic level signals and for switching in response to a voltage change in said positive voltage logic level signals; said first and second transistor means having first and second transistor outputs, respectively; third and fourth transistor means operably connected to said first and second transistor means outputs, respectively and to said output for switching in response to switching of said first and second transistor means; said third transistor means being connected to a negative voltage supply; said fourth transistor means being connected to ground; whereby in response to a positive voltage logic low at said input, said output produces a negative voltage logic low and in response to a positive voltage logic high at said input, said output produces a negative voltage logic high.

Claim 8

A level shifting network for shifting positive voltage logic levels to negative voltage logic levels comprising: an input and an output; first and second transistor means connected to said input for receiving positive voltage logic level signals and for switching in response to a voltage change in said positive voltage logic level signals; said first and second transistor means having first and second transistor outputs, respectively; third and fourth transistor means operably connected to said first and second transistor means outputs, respectively and to said output for switching in response to switching of said first and second transistor means; said third transistor means being connected to a negative voltage supply; said fourth transistor means being connected to ground; whereby in response to a positive voltage logic low at said input, said output produces a negative voltage logic low and in response to a positive voltage logic high at said input, said output produces a negative voltage logic high.

Claim 9

A level shifting network for shifting positive voltage logic levels to negative voltage logic levels comprising: an input and an output; first and second transistor means connected to said input for receiving positive voltage logic level signals and for switching in response to a voltage change in said positive voltage logic level signals; said first and second transistor means having first and second transistor outputs, respectively; third and fourth transistor means operably connected to said first and second transistor means outputs, respectively and to said output for switching in response to switching of said first and second transistor means; said third transistor means being connected to a negative voltage supply; said fourth transistor means being connected to ground; whereby in response to a positive voltage logic low at said input, said output produces a negative voltage logic low and in response to a positive voltage logic high at said input, said output produces a negative voltage logic high; said first transistor means including a base and a collector, said first transistor means base being connected to said input; said second transistor means including an emitter and a collector, said second transistor means emitter being connected to said input; said third transistor means including a base and an emitter, the base of said third transistor means being connected to the collector of said first transistor means; said fourth transistor means including a base and a collector, said fourth transistor means base being connected to said second transistor means collector; the emitter of said third transistor means being connected to said negative voltage supply; the collector of said fourth transistor means being connected to ground.

Claim 10

A level shifting network for shifting positive voltage logic levels to negative voltage logic levels comprising: an input and an output; first and second transistor means connected to said input for receiving positive voltage logic level signals and for switching in response to a voltage change in said positive voltage logic level signals; said first and second transistor means having first and second transistor outputs, respectively; third and fourth transistor means operably connected to said first and second transistor means outputs, respectively and to said output for switching in response to switching of said first and second transistor means; said third transistor means being connected to a negative voltage supply; said fourth transistor means being connected to ground; whereby in response to a positive voltage logic low at said input, said output produces a negative voltage logic low and in response to a positive voltage logic high at said input, said output produces a negative voltage logic high; said first transistor means including a base and a collector, said first transistor means base being connected to said input; said second transistor means including an emitter and a collector, said second transistor means emitter being connected to said input; said third transistor means including a base and an emitter, the base of said third transistor means being connected to the collector of said first transistor means; said fourth transistor means including a base and a collector, said fourth transistor means base being connected to said second transistor means collector; the emitter of said third transistor means being connected to said negative voltage supply; the collector of said fourth transistor means being connected to ground.

Claim 11

The network of claim 7 wherein: said third transistor means includes a collector; said fourth transistor means includes an emitter; and further including a diode connected between said third transistor means collector and said fourth transistor means emitter.

Claim 12

A level shifting network for shifting negative voltage logic levels to positive voltage logic levels comprising: a differential amplifier having first and second bias inputs, a first solely DC coupled input and an output; a first transistor having a base, an emitter and a collector, said first transistor base being connected to said differential amplifier output whereby in response to a negative voltage logic high at said first solely DC coupled differential amplifier input, said first transistor is non-conducting and in response to a negative voltage logic low at said first solely DC coupled input, said first transistor is conducting; a level shifting network output; a second transistor including a base, an emitter and a collector, said second transistor base being connected to said first transistor emitter for outputting to said level shifting network output a positive voltage logic low upon conduction of said first transistor; a third transistor including a base, an emitter and a collector, said third transistor base being connected to said first transistor collector for outputting to said level shifting network output a positive voltage logic high upon non-conduction of said first transistor.

Claim 13

A level shifting network for shifting negative voltage logic levels to positive voltage logic levels comprising: a differential amplifier having first and second bias inputs, a first solely DC coupled input and an output; a first transistor having a base, an emitter and a collector, said first transistor base being connected to said differential amplifier output whereby in response to a negative voltage logic high at said first solely DC coupled differential amplifier input, said first transistor is non-conducting and in response to a negative voltage logic low at said first solely DC coupled input, said first transistor is conducting; a level shifting network output; a second transistor including a base, an emitter and a collector, said second transistor base being connected to said first transistor emitter for outputting to said level shifting network output a positive voltage logic low upon conduction of said first transistor; a third transistor including a base, an emitter and a collector, said third transistor base being connected to said first transistor collector for outputting to said level shifting network output a positive voltage logic high upon non-conduction of said first transistor.

Claim 14

The network of claim 9 wherein said second transistor collector is connected to said third transistor emitter through a diode.

Claim 15

The network of claim 10 including a constant current source connected to said differential amplifier.

Claim 16

The network of claim 10 wherein said second transistor emitter is connected to ground and said third transistor collector is connected to a positive voltage supply.

Claim 17

The network of claim 9 wherein: a negative voltage supply is connected to said second solely DC coupled input.

Claim 18

The network of claim 9 further including: second and third transistor comprising said differential amplifier; said second transistor having a collector comprising said differential amplifier output such that said first transistor base is connected to said second transistor collector; said third transistor having a base connected to said second solely DC coupled input; and a negative voltage supply connected to said second solely DC coupled input.

Claim 19

The network of claim 14 further including: a constant current source connected to said differential amplifier comprising a voltage supply and a transistor connected to said voltage supply.